Renewable energy has become the most prominent source of energy to reduce carbon emissions around the globe. Undoubtedly, hydro energy is very much clean energy among other sources. In Bangladesh, hydro energy is available only in a specific southern area contributing several hundred megawatts to the national grid. This paper devotes to assessing the capacity and practicability of a hydropower plant to boost the power output by implementing the combined cycle hydropower system. The proposed method has been developed by 1) studying the existing plant based on surveyed data, 2) selecting the site for installing the hydrokinetic turbine, 3) designing with consideration of numerous constraints of inter dependability, and 4) creating a prototype model to ensure the practicability. Preliminary results show that a significant amount of additional electric energy can be generated from the plant with higher efficiency.

The involvement of assistive robot in every aspect of our life is immensely increasing in today's world. In this paper, a line following robot to assist an office is developed which can securely transfer hard copy of office file, tea snacks etc from one table to another inside an office autonomously as per user direction. Anybody can call the robot from any table by pressing a PUSH button. As a response of calling, the robot will come to the caller table following a path and a locker placed in the robot will be unlocked automatically. The caller then placed the file or any other materials in the locker and can direct the robot to another table by pressing another push button. The locker will not open until the robot reach at directed table to ensure the security. The robot also can detect obstacles and can produce alarm if someone stands in its path. The robot smoothly follows the path with the PID algorithm. The main components that are used to construct the robot are microcontroller, IR sensor module, RF Tx-Rx module, ultrasonic sensor, buzzer and DC motor. In every office there required a peon to transfer the files or other materials whereas they have to perform other tasks too. This robot can be useful to decrease the workload of office peons to involve him with more essential works.

Autonomous driving has emerged as a rapidly advancing field in both industry and academia over the past decade. Among the enabling technologies, computer vision (CV) has demonstrated high accuracy across various domains, making it a critical component of autonomous vehicle systems. However, CV tasks are computationally intensive and often require hardware accelerators to achieve real-time performance. Field Programmable Gate Arrays (FPGAs) have gained popularity in this context due to their reconfigurability and high energy efficiency. Numerous researchers have explored FPGA-accelerated CV solutions for autonomous driving, addressing key tasks such as lane detection, pedestrian recognition, traffic sign and signal classification, vehicle detection, object detection, environmental variability sensing, and fault analysis. Despite this growing body of work, the field remains fragmented, with significant variability in implementation approaches, evaluation metrics, and hardware platforms. Crucial performance factors, including latency, throughput, power consumption, energy efficiency, detection accuracy, datasets, and FPGA architectures, are often assessed inconsistently. To address this gap, this paper presents a comprehensive literature review of FPGA-accelerated, vision-based autonomous driving systems. It systematically examines existing solutions across sub-domains, categorizes key performance factors and synthesizes the current state of research. This study aims to provide a consolidated reference for researchers, supporting the development of more efficient and reliable next generation autonomous driving systems by highlighting trends, challenges, and opportunities in the field.

Hardware Trojan detection through side-channel analysis in physical chips is very challenging due to the presence of manufacturing process variations. Numerous Trojan detection approaches are in the literature. However, most of them are limited to netlist level identification and unable to explain the process variation issue in post-silicon chips. In this work, we propose a new detection technique with delay side-channel analysis that can detect all types of Trojans under the presence of high process variations. The technique is termed as zero delay deviation (ZDD) that is capable of diminishing the effect of all variations and other noise sources to identify the Trojan presence in chips. The ZDD approach is achieved by 1) a novel equal-delay circuit partitioning, 2) placing a highly secured camouflaged ring oscillator PUF per partition to generate equal-delay challenge-response pairs that delivers the knowledge of variation trends, 3) generating Identical Delay (ID) neighboring pairs for both, partitions and PUF designs that ensure nullifying the variation effects upon comparing them. The ZDD is examined through an intra-referencing of ID pairs with PUF-RD pairs in ISCAS’85 and 89 benchmarks. 10,000 virtual chips are generated by Monte Carlo simulation considering all physical characteristics of a real chip. Results demonstrate that the proposed approach can successfully detect Trojans even if it consists of a single gate. A comparison to the state-of-the-art shows the method superiority over others.

Advanced Encryption Standard (AES) is the most secured ciphertext algorithm that is unbreakable in a software platform’s reasonable time. AES has been proved to be the most robust symmetric encryption algorithm declared by the USA Government. Its hardware implementation offers much higher speed and physical security than that of its software implementation. The testability and hardware Trojans are two significant concerns that make the AES chip complex and vulnerable. The problem of testability in the complex AES chip is not addressed yet, and also, the hardware Trojan insertion into the chip may be a significant security threat by leaking information to the intruder. The proposed method is a dual-mode self-test architecture that can detect the hardware Trojans at the manufacturing test and perform an online parametric test to identify parametric chip defects. This work contributes to partitioning the AES circuit into small blocks and comparing adjacent blocks to ensure self-referencing. The detection accuracy is sharpened by a comparative power ratio threshold, determined by process variations and the accuracy of the built-in current sensors. This architecture can reduce the delay, power consumption, and area overhead compared to other works.