Junliang Shang

Mr. Junliang Shang

orcid

Research Focus & Metrics

Academic Career Length

2Years (2025-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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17 October 2025 in Semiconductor Science and Technology
Verified
Journal Article
Closed access
WZWenting Zhang
Wenting Zhang
SLShuang Li
Shuang Li
JSJunliang Shang
Junliang Shang
DMDongping Ma
Dongping Ma
MMMengqi Ma
Mengqi Ma
HLHu Liu
Hu Liu
Research on inverters that utilize organic field-effect transistors has garnered significant attention in recent years. Currently, most organic complementary metal–oxide semiconductor (CMOS)-like circuits use planar organic field-effect transistors as switching devices. However, due to limitations in fabrication processes, the channel lengths of these planar transistors are typically at the micrometer scale. This often leads to challenges such as high operating voltages and low intermediate logic levels in CMOS-like inverters built with these transistors. This paper proposes a CMOS-like inverter based on vertical organic field-effect transistors. The input and output characteristics of this inverter were numerically analyzed using the TCAD (Silvaco-Mixedmode) simulation tool. Thanks to the ultrashort nanometer-scale channels of vertical organic field-effect transistors, this inverter achieved a low operating voltage of 1.5 V and an intermediate logic value of 0.72 V.

20 February 2025 in Applied Sciences
Verified
Journal Article
Open access
PDF file
WZWenting Zhang
Wenting Zhang
JSJunliang Shang
Junliang Shang
SLShuang Li
Shuang Li
HLHu Liu
Hu Liu
MMMengqi Ma
Mengqi Ma
DMDongping Ma
Dongping Ma
In this work, floating-gate organic field-effect transistor memory using the n-type semiconductor poly-{[N,N′-bis(2-octyldodecyl) naphthalene-1,4,5,8-bis (dicarbo- ximide)-2,6-dili]-alt-5,5′-(2,2′-bithiophene)} (N2200) as a charge-trapping layer is presented. With the assistance of a technology computer-aided design (TCAD) tool (Silvaco-Atlas), the storage characteristics of the device are numerically simulated by using the carrier injection and Fower–Nordheim (FN) tunneling models. The shift in the transfer characteristic curves and the charge-trapping mechanism after programming/erasing (P/E) operations under different P/E voltages and different pulse operation times are discussed. The impacts of different thicknesses of the tunneling layer on storage characteristics are also analyzed. The results show that the memory window with a tunneling layer thickness of 8 nm is 16.1 V under the P/E voltage of ±45 V, 5 s. After 1000 cycle tests, the memory shows good fatigue resistance, and the read current on/off ratio reaches 103.