In this paper, an In_0.53Ga_0.47As electron–hole bilayer tunnel field-effect transistor (EHBTFET) with a dual-metal left-gate and an N⁺-pocket (DGNP-EHBTFET) is proposed and systematically studied by means of numerical simulation. Unlike traditional transverse EHBTFETs, the proposed DGNP-EHBTFET can improve device performance without sacrificing the chip density, and can simplify the manufacturing process. The introduction of the dual-metal left-gate and the N⁺-pocket can shift the point-tunneling junction and adjust the energy band and the electric field in it, aiming to substantially degrade the OFF-state current (I_OFF) and maintain good ON-state performance. Moreover, the line tunneling governed by the tunneling-gate and the right-gate can further regulate and control I_OFF. By optimizing various parameters related to the N⁺-pocket and the gate electrodes, DGNP-EHBTFET’s I_OFF is reduced by at least four orders of magnitude, it has a 75.1% decreased average subthreshold swing compared with other EHBTFETs, and it can maintain a high ON-state current. This design greatly promotes the application potential of EHBTFETs.

With ongoing advancements, heterojunction structures have been widely adopted in the memory domain, delivering enhanced performance and superior properties beyond those offered by single-layer thin films. In particular, among various organic field-effect transistor memory (OFETM) technologies, heterojunction-based OFETMs have emerged as one of the most promising data storage technologies, with applications ranging from sensory and storage to neuromorphic computing. Heterostructure-based OFETMs can achieve a memory window of up to 90 V, a high current on/off ratio of $10^7$, and retention characteristics exceeding 10 years. Furthermore, these devices exhibit rapid programming/erasing speeds in the millisecond to microsecond range (e.g., as fast as 1 $\mu s$) and can operate at low voltages (typically below 10 V). However, heterostructure-based OFETMs face significant stability challenges that critically impact their performance and practical use. Given that stability is a key performance metric for OFETMs, researchers are actively working to enhance the reliability of heterojunction-based memory devices. Consequently, a diverse range of heterostructures has been developed---including organic-inorganic heterostructures, inorganic-inorganic hybrids, and organic-organic heterostructures---each demonstrating significant potential across various applications. This review discusses the research process of OFETMs utilizing organic heterojunctions, emphasizing the fundamental physical mechanisms and key performance parameters that contribute to their exceptional capabilities.

To give consideration to both chip density and device performance, an In_0.53Ga_0.47As vertical electron–hole bilayer tunnel field effect transistor (EHBTFET) with a P⁺-pocket and an In_0.52Al_0.48As-block (VPB-EHBTFET) is introduced and systematically studied by TCAD simulation. The introduction of the P⁺-pocket can reduce the line tunneling distance, thereby enhancing the on-state current. This can also effectively address the challenge of forming a hole inversion layer in an undoped InGaAs channel during device fabrication. Moreover, the point tunneling can be significantly suppressed by the In_0.52Al_0.48As-block, resulting in a substantial decrease in the off-state current. By optimizing the width and doping concentration of the P⁺-pocket as well as the length and width of the In_0.52Al_0.48As-block, VPB-EHBTFET can obtain an off-state current of 1.83 × 10⁻¹⁹ A/μm, on-state current of 1.04 × 10⁻⁴ A/μm, and an average subthreshold swing of 5.5 mV/dec. Compared with traditional InGaAs vertical EHBTFET, the proposed VPB-EHBTFET has a three orders of magnitude decrease in the off-state current, about six times increase in the on-state current, 81.8% reduction in the average subthreshold swing, and stronger inhibitory ability on the drain-induced barrier-lowering effect (7.5 mV/V); these benefits enhance the practical application of EHBTFETs.

Research on inverters that utilize organic field-effect transistors has garnered significant attention in recent years. Currently, most organic complementary metal–oxide semiconductor (CMOS)-like circuits use planar organic field-effect transistors as switching devices. However, due to limitations in fabrication processes, the channel lengths of these planar transistors are typically at the micrometer scale. This often leads to challenges such as high operating voltages and low intermediate logic levels in CMOS-like inverters built with these transistors. This paper proposes a CMOS-like inverter based on vertical organic field-effect transistors. The input and output characteristics of this inverter were numerically analyzed using the TCAD (Silvaco-Mixedmode) simulation tool. Thanks to the ultrashort nanometer-scale channels of vertical organic field-effect transistors, this inverter achieved a low operating voltage of 1.5 V and an intermediate logic value of 0.72 V.

In this work, floating-gate organic field-effect transistor memory using the n-type semiconductor poly-{[N,N′-bis(2-octyldodecyl) naphthalene-1,4,5,8-bis (dicarbo- ximide)-2,6-dili]-alt-5,5′-(2,2′-bithiophene)} (N2200) as a charge-trapping layer is presented. With the assistance of a technology computer-aided design (TCAD) tool (Silvaco-Atlas), the storage characteristics of the device are numerically simulated by using the carrier injection and Fower–Nordheim (FN) tunneling models. The shift in the transfer characteristic curves and the charge-trapping mechanism after programming/erasing (P/E) operations under different P/E voltages and different pulse operation times are discussed. The impacts of different thicknesses of the tunneling layer on storage characteristics are also analyzed. The results show that the memory window with a tunneling layer thickness of 8 nm is 16.1 V under the P/E voltage of ±45 V, 5 s. After 1000 cycle tests, the memory shows good fatigue resistance, and the read current on/off ratio reaches 10³.