This paper presents a drift-resilient time-based resistive sensor interface in a 0.18-μm CMOS technology. The interface is built around only two oscillators, a phase detector, a digital filter, and a digital-to-analog converter (DAC), resulting in a simple first-order Delta-Sigma design with a predictable transfer function. The highly digital approach not only results in a small area but also implies that only a few analog circuits are sensitive to drift. The holistic drift-resilience strategy implemented combines time-based chopping and voltage-controlled oscillator (VCO) tuning to remove the dc and low-frequency errors introduced by VCO nonidealities and drift. These techniques do not introduce a significant area and power overhead. Silicon measurements show that the proposed bang-bang phase-locked loop (BBPLL)-based sensor interface exhibits ppm-level gain drift and offset drift for the entire -40 ° C-175 ° C temperature range while using a single-temperature calibration scheme and no external accurate references nor components for this drift stability. The interface provides a 15-effective number of bits conversion for a 100-ms conversion time and consumes 3.41 mW of power and occupies only 0.23 mm² of the active area.

The evolution of electronics towards compact and highly energy-efficient systems requires joint efforts in developing both innovative system architectures and novel devices. Recent developments show that time-based sensor interfaces yield highly-digital architectures, which are compatible with advanced silicon CMOS at highly-scaled technology nodes. Advancements in CMOS time-based sensor interfaces show that new circuit techniques can help to increase performance and robustness. Furthermore, these architectures have successfully been implemented in carbon nanotube technology, a promising technology to further reduce the energy consumption in electronics. In addition, CNTs are excellent candidates to be functionalized as sensors, and can potentially improve the energy efficiency of sensors and sensor interfaces for future autonomy-demanding applications. This paper presents an overview of time-based sensor interfaces implemented in CMOS and CNT technologies, allowing for scalable and robust designs. Several CMOS and VLSI-compatible CNFET-based sensor interface circuits have been fabricated and validated through measurements, demonstrating the feasibility of these solutions.

Open-source tools and PDKs facilitate the design, implementation and silicon validation of integrated circuits, circumventing the traditional barriers associated with this field. Power integrated circuits, conversely, are increasingly relevant in modern systems targeting energy-efficient applications. In this study, the design of a power integrated circuit is examined from the perspective of open-source silicon design, which has recently emerged as a feasible approach for acquiring functional silicon-proven designs with low entry barriers. Utilizing this workflow, we showcase the complete design, simulation, layout, and experimental validation of an integrated multilevel dc-dc converter: specifically, a three-level flying capacitor buck converter. Our system converts 3.3V dc bus levels to 1.8V and below, for a measured peak efficiency of 89.3%. The maximum measured load current is 250mA, using two conversion cores operating in interleaved mode. The system has been implemented in 6.27mm ² of active area using the Skywater 130nm standard CMOS technology open-source PDK.

In this study, we present the design, simulation, and implementation of a DC-DC synchronous buck converter utilizing IISB’s 2 $\mathrm{\mu }$m 4H-silicon carbide (SiC) complementary metal–oxide–semiconductor (CMOS) technology. The converter is designed to meet the demands of modern integrated circuits, particularly in the field of integrated power management. The SiC technology offers enhanced performance and reliability at high temperatures, making it especially suitable for applications that operate in these conditions, including automotive systems, and aerospace, among others. The power transistors and gate drivers are fully integrated on-chip, optimizing efficiency and minimizing footprint. Additionally, the study contributes to the understanding of SiC technology and its application in integrated circuit design. Simulation results demonstrate a peak efficiency of 86.6% at 120 mA load current and 84.8% at 300 mA load current, showing the converter performance under different operating conditions. Furthermore, at high temperatures (295 °C), the converter achieves an efficiency of 89.6%, demonstrating its robustness and versatility in extreme environments. These findings contribute to the advancement of integrated circuit design and facilitate advancements in more efficient and robust power management solutions.

This paper presents the drift error analysis of the integrated resistive sensor interfaces and its improvement using the drift-cancellation techniques. This paper focuses on the highly digital time-domain bang-bang phase-locked loop-based architectures that-when ideal-are intrinsically resilient to the drift generated by environmental and circuit degradation effects. Nevertheless, for applications aiming at nearly zero drift, nonideal effects resulting from mismatch and nonlinearity are still creating a residual drift error of the order of 0.5% of the full scale. The feedback mechanisms of the architecture are studied under nonideal circuit conditions using system-level analysis and simulations. The residual drift error is canceled using the system-level time-based compatible techniques applied in an online fashion, without external references and with low power and area overhead due to their highly digital implementation. The system-level simulation results show that the drift error due to mismatch is attenuated within ±0.05% of the full scale, corresponding to a 10× improvement with respect to the previous publications.