Tiny machine learning (TinyML) demands the development of edge solutions that are both low-latency and power-efficient. To achieve these on System-on-Chip (SoC) FPGAs, co-design methodologies, such as hls4ml, have emerged aiming to speed up the design process. In this context, fast estimation of FPGA’s utilized resources is needed to rapidly assess the feasibility of a design. In this paper, we propose a resource estimator for fully customized (bespoke) multilayer perceptrons (MLPs) designed through the hls4ml workflow. Through the analysis of bespoke MLPs synthesized using Xilinx High-Level Synthesis (HLS) tools, we developed resource estimation models for the dense layers’ arithmetic modules and registers. These models consider the unique characteristics inherent to the bespoke nature of the MLPs. Our estimator was evaluated on six different architectures for synthetic and real benchmarks, which were designed using Xilinx Vitis HLS 2022.1 targeting the ZYNQ-7000 FPGAs. Our experimental analysis demonstrates that our estimator can accurately predict the required resources in terms of the utilized Look-Up Tables (LUTs), Flip-Flops (FFs), and Digital Signal Processing (DSP) units in less than 147 ms of single-threaded execution.

Many-accelerator platforms have been introduced for maximizing FPGA's throughput. However, as the high saturation rate of the FPGA's on-chip memories limits the number of synthesized accelerators, frameworks for Dynamic Memory Management (DMM) that allow the synthesized designs to allocate/de-allocate on-chip memory resources during run-time have been suggested. Although, those frameworks manage to increase the accelerators’ density by minimizing the utilized memory resources, the parallel execution of many-accelerators may cause severe memory fragmentation and thus memory allocation failures. In this work, a framework that optimizes the memory usage by performing memory defragmentation operations in HLS many-accelerator architectures that share on-chip memories is proposed. Experimental results highlight the effectiveness of the proposed solution to eliminate memory allocation failures due to memory fragmentation, reduce memory allocation failures up to 32% on average and decrease the memory size requirements up to 5% with controllable latency and resource utilization overhead.

Millimeter wave (mmWave) frequencies offer broad channel-bandwidths in 6G Radio Access Networks (RANs), but can be severely limited by channel outages and blockage phenomena in realistic non-line of sight field-environments. This work experimentally presents the first, outdoor 3 × 1 Fiber Wireless (FiWi) mmWave Distributed Antenna System (DAS) across 7 km fiber-distances and 30 m wireless radio links, Software Defined Controlled (SDN) Coordinated Multipoint (CoMP) scheduled transmissions from three rooftop antennas to a mobile UE. The proposed system relies on wavelength-tunable transmissions through an all-passive, energy-efficient 32 × 32 AWGR and an algorithmic workflow that continuously monitors the FiWi link status, allowing for a scalable solution with even higher number of antennas and interfaces. The system is thoroughly evaluated in the physical layer, exhibiting up to 4.5 Gb/s data-rate at a $25^{o}$ degree beam-width and latency down to less than 0.2 ms. Continuous, SDN-controlled CoMP transmission is initially presented in pre-defined time-slots that alternate the three FiWi paths every 1 s with high 14.4 dB isolation and 25 $\mu$s switching time. Unobstructed connectivity scenario is also experimentally presented, where an intentional mmWave blockage and link outage triggers a zero-touch re-routing and scheduling of upcoming traffic to the UE via an alternate path, selected in a round robbin manner. Finally, real-time streaming services and computation offloading of typical 6G applications at a nearby MEC server confirm the capability of the proposed system to provide high-availability services, shaping a promising roadmap for self-organizing 6G mmWave networks.

In the emerging era of 5G+/6G, flexibility and autonomous operation of Radio Access Networks (RANs) without strict bandwidth limitations or energy-waste trade-offs are actively being pursued to satisfy the immense capacity demands and time-varying nature of mobile networks. The current work reports the first field trial of a fully automated, Software Defined Network (SDN) controlled hybrid Fiber Wireless (FiWi) Free Space Optics (FSO)/millimeter-wave (mmWave) X-haul link with a record-high data-rate up to 100 Gb/s using real-time traffic. Specifically, the hybrid FiWi X-haul link relies on wavelength-tunable transmissions across an O-band FSO link or a C-band FiWi mmWave channel, being dynamically allocated and wavelength-routed by means of an all-passive O-band/C-band diplexer. A complete SDN algorithmic workflow that periodically polls the status of the wireless channel, triggering a fully automated handover to the optimum functional channel upon adverse weather conditions or channel outages is developed, relying exclusively on open-source and inter-operable SDN agent and network controller solutions. The hybrid link is initially evaluated at a cascaded transmission across a 1 km fiber and a 25 m-indoor wireless stages, achieving a periodic time-slotted operation with 25 $\mu$s beam-switching time, O/C-band crosstalk less than −30 dB and wide open eye diagrams with 6.8 dB Extinction Ratio (ER). Finally, the hybrid link is benchmarked in a 24-hour long, automated, zero-touch, outdoor setup with 1km fiber and 50 m wireless distance, providing robust rooftop-to-rooftop communication across two neighboring buildings with up to 100 Gb/s capacity, transporting real-time services and 4K-UHD video streaming with uninterrupted operation under both daylight and nighttime turbulent conditions with 5 Beaufort wind speed. The proposed real-time, automated hybrid FiWi FSO/mmWave link is the first to break the 10 Gb/s barrier of conventional edge networks, shaping a promising hardware-software X-haul solution towards survivable 5G+/6G RANs.

Printed Electronics (PE) set up a new path for the realization of ultra low-cost circuits that can be deployed in everyday consumer goods and disposables. In addition, PE satisfy requirements such as porosity, flexibility, and conformity. However, the large feature sizes in PE and limited device counts incur high restrictions and increased area and power overheads, prohibiting the realization of complex circuits. As a result, although printed Machine Learning (ML) circuits could open new horizons and bring "intelligence" in such domains, the implementation of complex classifiers, as required in target applications, is hardly feasible. In this paper, we aim to address this and focus on the design of battery powered printed Multilayer Perceptrons (MLPs). To that end, we exploit fully-customized circuit (bespoke) implementations, enabled in PE, and propose a hardware-aware neural minimization framework dedicated for such customized MLP circuits. Our evaluation demonstrates that, for up to 3% accuracy loss, our co-design methodology enables, for the first time, battery-powered operation of complex printed MLPs.