This paper presents a fully integrated G_m–C low pass filter (LPF) based on a current steering G_m reduction-tuning technique, specifically designed to operate as the output stage of a SoC lock-in amplifier. To validate this proposal, a first-order and a second-order single-ended topology were integrated into a 1.8 V to 0.18 µm CMOS (Complementary Metal-Oxide-Semiconductor) process, showing experimentally a tuneable cutoff frequency that spanned five orders of magnitude, from tens of mHz to kHz, with a constant current consumption (below 3 µA/pole), compact size (<0.0140 mm²/pole), and a dynamic range better than 70 dB. Compared to state-of-the-art solutions, the proposed approach exhibited very competitive performances while simultaneously fully satisfying the demanding requirements of on-chip portable measurement systems in terms of highly efficient area and power. This is of special relevance, taking into account the current trend towards multichannel instruments to process sensor arrays, as the total area and power consumption will be proportional to the number of channels.

Cavity photons and ferromagnetic spin excitations can exchange information coherently in hybrid architectures, at speeds set by their mutual coupling strength. Speed enhancement is usually achieved by optimizing the geometry of the electromagnetic cavity. Here we show that the geometry of the ferromagnet also plays a role, by setting the fundamental frequency of the magnonic resonator. Using focused ion-beam patterning, we vary the aspect ratio of different Permalloy samples reaching operation frequencies above 10 GHz while working at low external magnetic fields. Additionally, we perform broadband ferromagnetic resonance measurements and cavity experiments that demonstrate that the light-matter coupling strength can be estimated using either open transmission lines or resonant cavities, yielding very good agreement. Finally, we describe a simple theoretical framework based on electromagnetic and micromagnetic simulations that successfully accounts for the experimental results. This approach can be used to design hybrid quantum systems exploiting magnetostatic mode excited in ferromagnets of arbitrary size and shape and to tune their operation conditions.

This paper presents the design and postlayout simulation results of a capacitor-less low dropout (LDO) regulator fully integrated in a low-cost standard 180 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology which regulates the output voltage at 1.2 V from a 3.3 to 1.3 V battery over a −40 to 120 °C temperature range. To meet with the constraints of system-on-chip (SoC) battery-operated devices, ultralow power (I_q = 8.6 µA) and minimum area consumption (0.109 mm²) are maintained, including a reference voltage V_ref = 0.4 V. It uses a high-gain dynamically biased folded-based error amplifier topology optimized for low-voltage operation that achieves an enhanced regulation-fast transient performance trade-off.

In this paper we present the experimental characterization of active components of a standard 65nm CMOS technology for a temperature range from 313K to 5K, analyzing the variation of the main parameters over temperature and voltage, recovering their main parameters (threshold voltage Vttth, transconductance Gm and channel conductance GDS). The measurement has been carried out wire-bonding the bare dies with the devices to a dedicated PCB that has been placed inside a dilution refrigerator. The ID-VDS curves for both NMOS and PMOS transistors shows an increase of ID in the cryogenic regime that is more relevant for high values of VGS because for lower values it is partially compensated by the variation of Vttth. Also, a kink is observed in these curves for high VDS values, caused by the bulk current generated by impact ionization at the drain combined with the increased resistivity of the frozen-out substrate. The transconductance Gm reaches non-zero values for higher VGS as T decreases and then peaking to higher values in the cryogenic regime. In turn, GDS increases for increasing T, following the behaviour observed for ID. Both results are in accordance to other thermal characterizations carried out on CMOS transistors in different technologies.

A low‐power 0.18 µm CMOS capacitor‐less low‐dropout voltage regulator for battery‐operated portable devices is presented. A high‐gain telescopic cascode‐compensated amplifier is used to attain a stable topology with good static performances, while a very simple dynamic biasing circuit significantly enhances transient performances with no quiescent current penalty. Post‐layout results show a 1.8 V output voltage from a 3.6 to 1.9 V battery input voltage, delivering a 50 mA load current over a 100 pF load. The quiescent current is only 7 µA, the line and load regulations are, respectively, 0.039 mV/V and 0.17 mV/mA, and settling times are lower than 3.9 µs at full load transient.

This paper presents a low-power fully integrated 0.18 μm CMOS Low-Dropout (LDO) Voltage Regulator for battery-operated portable devices. A single stage high-gain telescopic cascode-compensated amplifier is used to attain good static performances, while thanks to a very simple dynamic bias circuit, transient performances are significantly enhanced with no quiescent current penalty. Results validate a 1.8 V output voltage from a 3.6 V to 1.9 V battery input voltage, delivering a load current of 50 mA over a 100 pF load. The quiescent current is only 7 μA, the line and load regulation are respectively 0.159 mV/V and 0.017 mV/mA, and settling times are lower than 4.6 μs at full load transient.