This paper presents the implementation of a wearable wireless sensor network aimed at monitoring harmful gases in industrial environments. The proposed solution is based on a customized wearable sensor node using a low-power low-rate wireless personal area network (LR-WPAN) communications protocol, which as a first approach measures CO₂ concentration, and employs different low power strategies for appropriate energy handling which is essential to achieving long battery life. These wearables nodes are connected to a deployed static network and a web-based application allows data storage, remote control and monitoring of the complete network. Therefore, a complete and versatile remote web application with a locally implemented decision-making system is accomplished, which allows early detection of hazardous situations for exposed workers.

Dual-phase lock-in amplifiers (LIAs) are designed to extract information (amplitude and phase) from signals buried in high noise levels. In spite of their popularity, their use has been traditionally limited to input sinusoidal waves with symmetric power supplies. This paper presents an algorithm that enables single-supply analog LIAs to properly process input square waves. Formed by linear equations, its computational implementation is much simpler than that of the traditional sinusoidal algorithm. Moreover, applied to battery-operated microcontrolled systems where square signals can be generated by the embedded microcontroller, it presents intrinsic advantages such as simplicity, versatility, and reduction in power and size. Experimental results validate the proposed algorithm, confirming its enormous possibilities in sensing applications.

This paper presents the design and experimental characterization of two lock-in amplifier (LIA) prototypes integrated in a 0.18-μm CMOS process with a single supply voltage of 1.8 V. As opposed to previously reported integrated LIAs, synchronous rectification is performed in the current domain, providing key features such as low power (<;420 μW) and reduced area (0.013 mm ² ), with a dynamic reserve better than 35 dB and less than 5% relative error in the signal recovery. The principle of operation of each prototype is presented and their performance is compared with previous implementations, validating their suitability for low-cost portable applications.

This paper presents a fast-settling compact feedforward automatic-gain-control (AGC) circuit suitable for use in wireless local-area network receivers with orthogonal frequency-division multiplexing (OFDM). The use of these signals introduces stringent settling-time constraints which limit the use of traditional closed-loop feedback amplifiers. Furthermore, the amplitude detection of OFDM signals cannot be performed by a typical peak detector (PD) due to their high peak-to-average power ratio; as a consequence, a novel fast-settling PD is employed to solve this task. The AGC has been implemented in a low-cost 0.35-μm CMOS technology. Supplied at 1.8 V, it operates with a power consumption of 2.4 mW at frequencies as high as 100 MHz, while its gain ranges from 0 to 22 dB in 2-dB steps through a 5-b word. The settling time of the circuit is below 2.4 μs (three symbols).

This paper presents a new low-voltage pseudodifferential continuous-time CMOS transconductor for wide-band applications. The proposed cell is based on a feedforward cancellation of the input common-mode signal and keeps the input common mode voltage constant, while the transconductance is easily tunable through a continuous bias voltage. Linearity is preserved during the tuning process for a moderate range of transconductance values. Measurements results for a 0.35-m CMOS design show a 1:2 tuning range with total harmonic distortion figures at 10 MHz below 58 dB over the whole range up to a 200- differential output current. The proposed cell consumes less than 1.1 mW from a single 1.8-V supply.

The development of real-time, reliable, low-cost automatic phonocardiogram (PCG) analysis systems is critical for the early detection of cardiovascular diseases (CVDs), especially in countries with limited access to primary health care programs. Once the raw PCG acquired by the stethoscope has been preprocessed, the first key task is its segmentation into the fundamental heart sounds. For this purpose, an optimized hardware implementation of the segmentation algorithm is essential to attain a computer-aided diagnostic system based on PCGs. This article presents the optimization of a U-Net-based segmentation algorithm for its implementation in a low-end field-programmable gate array (FPGA) using low-resolution fixed-point data types. The optimization strategies seek to reduce the system latency while maintaining a constrained consumption of FPGA resources, aiming for a real-time response from the stethoscope data acquisition to the CVD detection. Experimental results prove a 64% decrease in latency compared to a baseline version, a 3.9% reduction of block random access memory (BRAM), which is the limiting resource of the design, and a 70% reduction in energy consumption. To the best of our knowledge, this is the first work to exhaustively study different optimization strategies for implementing a large 1-D U-Net-based model, achieving real-time fully characterized performance.