Recently, experimental results have demonstrated that perpendicular magnetic tunnel junction (p-MTJ) with the antiferromagnetic(AFM)/ferromagnetic (FM)/oxide structure can achieve field-free spin-orbit torque (SOT) switching since the AFM metal strip can not only generate the SOT, but also provide an exchange bias (HEX), making it suitable for practical applications. However, owing to that the HEX is weak, such field-free SOT switching is incomplete, thus resulting in severe switching reliability. In addition, a large SOT switching current (ISOT) is also required, leading to high switching energy dissipation. In this paper, to address these issues, the voltage-controlled magnetic anisotropy (VCMA) is introduced to assist the SOT switching, and such novel switching method is referred as voltage-gated SOT (VGSOT). First, we develop a physics-based compact model for the three-terminal VGSOT-MTJ device, which includes three modules, i.e., the electrical module, the tunnel magnetoresistance module and the dynamic switching module. Then, the impact of the VCMA effect on the field-free SOT switching is investigated by solving a modified Landau-Lifshitz-Gilbert (LLG) equation with consideration of the VCMA, SOT and HEX. Simulation results show that thanks to the introduction of the VCMA effect, the critical ISOT can be reduced greatly, and the incomplete field-free SOT switching can be completed. With further analysis, we obtain a special switching condition, under which complete SOT field-free switching can be achieved with a shortest path and ultra-low power. Moreover, a novel write pulse scheme is proposed to achieve high speed and reliability.

Recently, several magnetic tunnel junction (MTJ)-based non-volatile ternary content-addressable memory (NV-TCAM) cells have been proposed to realize zero standby power. However, they still suffer from low reliability and high power consumption during search operations. To address these issues, we propose a novel MTJ-based NV-TCAM cell, which is composed of 15 transistors and 4 MTJs (15T-4MTJ). By utilizing the differential MTJs with complementary states and positive feedback of cross-coupled inverters for sensing, the proposed 15T-4MTJ NV-TCAM cell can significantly improve the search reliability. Moreover, owing to that there is no static current during search operations, only dynamic charging and discharging current, it can achieve ultra-low power consumption. In addition, by using only one transistor as the critical path between the match-line and GND, its switch delay can be shortened, thereby realizing high-speed search operations. Hybrid CMOS/MTJ simulation results of the 144-bit word circuit show that the proposed 15T-4MTJ NV-TCAM cell can obtain a smaller search error rate of 2.7%, a higher search speed of 0.17 ns, and a lower search energy of 0.17 fJ/bit/search in comparison with other MTJ-based NV-TCAM cells. On the other hand, its write energy of 1.589 pJ/bit is about 3.64x smaller than that of the previously proposed 10T-4MTJ NV-TCAM cell.

Recently, various magnetic non-volatile ternary content-addressable memory (MNV-TCAM) cells that use magnetic tunnel junctions (MTJs) as storage units have been proposed to realize zero standby power. However, they still suffer from low reliability and high power consumption for search operation. In addition, the restrictions on the ordering of the TCAM array required by the using of the priority encoder to resolve the multiple match problem due to the `X' results in large delay and high energy consumption for update operation. To address these issues, the novel MNV-TCAM cell is first proposed, aiming to achieve high-speed, low-power, and high-reliable search operation. In addition to the search data operation, it can realize a search length operation. By exploiting this search length operation, we then present circuit-level design of the MNV-TCAM with a priority-decision in memory technology, which can utilize the length information of matched words sorted in an arbitrary order to decide the highest-priority matched word by performing a three-phase search operation. It implies that the restrictions on the ordering can be eliminated, thus, improving the update speed and energy-efficiency. Finally, hybrid CMOS/MTJ simulations are performed to demonstrate its functionality and evaluate its performance in terms of search reliability, search speed, and search energy consumption.

Continued scaling of Complementary Metal Oxide Semiconductor (CMOS) integrated circuit technology is slowing down due to physical limitations, while the static power of CMOS based memory is increasing as the transistors shrink. As an alternative memory technology, the Spin Transfer Torque Magnetic RAM (STT-MRAM) remains limited to low-level, high-capacity caches because of the high write power and still unsatisfactory write access speed. Spin Orbit Torque MRAM (SOT-MRAM), which has been proposed to tackle this issue, still faces some issues including the poor read margin due to low Tunnel Magnetoresistance (TMR) and undesirable use of a magnetic field for deterministic switching. This article proposes a novel 3T2SOT (three Transistors and two SOT magnetic tunnel junctions) based field-free MRAM, which can achieve higher read speed and reliability by adopting a self-referencing scheme, and lower write power benefiting from an advanced switching mechanism. Detailed circuit-level simulation results show that the write latency of the proposed design can be reduced to 0.3 ns, and the write power is two orders of magnitude lower than STT-MRAM. Additionally, compared to SRAM, for 8 MB cache memory, the read speed of 3T2SOT MRAM is enhanced by 38.9%. Compared to conventional 2T1SOT MRAM, the read performance is similar and the read error rate is dropped by 96.1% at least.

Physical unclonable function (PUF) is an emerging hardware security primitive which is increasingly used to authenticate and identify Internet of Things (IoT) devices. Spin-transfer torque magnetoresistive random access memory (STT-MRAM) provides new opportunities for novel PUFs due to inherent randomness sources, such as process variations, stochastic switching, and chaotic magnetization. In this article, we propose a hybrid STT-MRAM/complementary metal-oxide semiconductor (CMOS)-based reconfigurable arbiter PUF (MPUF) with enhanced performance metrics in terms of reliability, uniqueness, and uniformity. This design has a mean intra-hamming distance (HD) of 0.147%, a mean inter-HD of 50.21%, and passes the National Institute of Standards and Technology (NIST) statistical tests. The proposed arbiter MPUF features distinct advantages, such as reconfigurable architecture, challenge-dependent stage delays, and huge challenge-response pair (CRP) space. Moreover, the robustness of the proposed MPUF against machine learning (ML)-based modeling attacks is tested using three ML algorithms, namely support vector machine (SVM), linear regression (LR), and multilayer perceptron (MLP). Results show that the proposed reconfigurable arbiter MPUF is resistant to ML attacks and minimizes the ML attack prediction accuracy to less than 65.12% without XOR and less than 44.34% with XOR. Meanwhile, the correlation power analysis demonstrates that the proposed MPUF is also resilient to side-channel attacks.

This article proposes two different magnetic nonvolatile-static random access memory (MNV-SRAM) cell circuits for low-power, high-speed, and high-reliable backup operation with a compact cell area. They employ perpendicular magnetic tunnel junctions (p-MTJs) as nonvolatile backup storage elements and explore the spin-orbit torque (SOT) with the assistance of the voltage-controlled magnetic anisotropy effect (VCMA), referred to voltage-gated SOT (VGSOT), to perform the backup operation. By using an antiferromagnetic (AFM) layer that provides both an exchange bias and the SOT, no external magnetic field is required, making it suitable for practical applications. In addition, owing to the aid of the VCMA effect, the critical SOT write current (I _SOT ) for 1-ns backup operation can be reduced significantly, thus resulting in high speed, low power consumption, and high reliability. Moreover, such resulted I _SOT allows to be driven by the cross-coupled inverters in the SRAM cell, instead of a dedicated write driver, thereby leading to low cell area overhead. By using a commercial CMOS 40-nm design kit and a physics-based VGSOT-MTJ model, we have demonstrated their functionalities and evaluated their performance. Compared with previous SOT-based MNV-SRAM cell circuits, the proposed MNV-SRAM cell circuits can achieve lower backup energy dissipation, smaller backup delay, lower backup error rate and less cell area overhead without the assistance of the external magnetic field.