Recently, several magnetic tunnel junction (MTJ)-based non-volatile ternary content-addressable memory (NV-TCAM) cells have been proposed to realize zero standby power. However, they still suffer from low reliability and high power consumption during search operations. To address these issues, we propose a novel MTJ-based NV-TCAM cell, which is composed of 15 transistors and 4 MTJs (15T-4MTJ). By utilizing the differential MTJs with complementary states and positive feedback of cross-coupled inverters for sensing, the proposed 15T-4MTJ NV-TCAM cell can significantly improve the search reliability. Moreover, owing to that there is no static current during search operations, only dynamic charging and discharging current, it can achieve ultra-low power consumption. In addition, by using only one transistor as the critical path between the match-line and GND, its switch delay can be shortened, thereby realizing high-speed search operations. Hybrid CMOS/MTJ simulation results of the 144-bit word circuit show that the proposed 15T-4MTJ NV-TCAM cell can obtain a smaller search error rate of 2.7%, a higher search speed of 0.17 ns, and a lower search energy of 0.17 fJ/bit/search in comparison with other MTJ-based NV-TCAM cells. On the other hand, its write energy of 1.589 pJ/bit is about 3.64x smaller than that of the previously proposed 10T-4MTJ NV-TCAM cell.

Sparse coding provides a powerful means to perform feature extraction on high-dimensional data and recently has attracted broad interest for applications. However, it still suffers from a big challenge to realize real-time energy-efficient feature extraction with conventional CPUs/GPUs owing to its highly intensive computation. Benefitting from the non-volatility, low power, high speed, great scalability and good compatibility with CMOS technology, spintronic devices, such as magnetic tunnel junction (MTJ) and domain wall motion (DWM) device, have been explored for applications, ranging from memory, logic, to neuromorphic computing. In this paper, we explore the possibility of hardware acceleration implementation of sparse coding algorithm with spintronic devices by a series of design optimizations across the algorithm, architecture, circuit and device. Firstly, one sparse coding algorithm is selected well-suited for parallelization and hardware acceleration. Then, a DWM based compound spintronic device (CSD) is engineered and modelled, which is envisioned to achieve multiple conductance states. Sequentially, a parallel architecture is presented based on a dense cross-point array of the proposed DWM based CSD, which can be envisioned to accelerate the selected sparse coding algorithm with a designed dedicated periphery read and write circuit owing to its massively parallel read and write operation. Experimental results show that the selected sparse coding algorithm can be accelerated by 1400× with the proposed parallel architecture in comparison with software implementation. Moreover, its energy dissipation is 8 orders of magnitude smaller than that with software implementation. Additionally, an artificial neural circuit (ANC) with the proposed DWM based CSD is also presented, which can achieve a multi-step transfer function. By using the proposed DWM based CSD as a single synapse and the proposed ANC as one neuron, a fully-forward-connected artificial neural network (ANN) is constructed to classify the learned feature vectors. And the recognition error rate can reach 7.25%.

The spin torque nano-oscillator (STNO) is a very promising candidate for next generation telecommunication systems due to its small size ~100 nm and high output frequency range. However, it still suffers low output power, usually smaller than µ W, and very high phase noise. Also, the modulation method for the STNO should be further developed. The frequency modulation and amplitude modulation method for STNO can be easily applied because of the non-linear nature of STNO, yet it is very rare to see the proposal of a phase modulation method. In this work, we propose a robust phase shift keying modulation method for STNO. Its feasibility is demonstrated with both theoretical and numerical analysis, and its robustness is investigated under room temperature thermal noise. It is shown that our proposed phase modulation method can tune the phase arbitrarily, while the modulation speed can be as fast as 10 ns at room temperature. Comparing with the other phase modulation method, our approach has advantages of larger phase tuning range and stronger robustness against thermal noise.

Magnetic Random Access Memory (MRAM) has enormous application potential in the aerospace field due to its nonvolatile, high speed, low power, and inherent radiation resistance characteristics. Due to its high sensing reliability, pre-charge differential sense amplifier (PCDSA) has been proposed and widely used in MRAM products. However, such PCDSA is based on traditional CMOS technology, and as the size of CMOS technology continues to shrink, its sensing result is easily affected by single event upset (SEU) or even the single event double node upset (SEDU). Recently, a TSC-PCDSA has been proposed to fully tolerate SEDU. However, it still suffers from slow speed, high power consumption and low reliability during normal sense operation. To address these issues, this paper proposes a novel PCDSA circuit that uses 6 three-input approximate C-elements (TACs) and 2 three-input standard C-elements (TSCs) to provide SEDU-tolerance. By reducing the number of transistors on the discharge path and increasing the difference in discharge current, the proposed PCDSA can achieve high speed, low power and high reliability. By using a physics-based STT-MTJ compact model and a commercial CMOS 40 nm design kit, hybrid simulations have been performed to demonstrate its functionality and evaluate its performance. Simulation results show that when the TMR is 150%, the width of N1-N12 is 480 nm and the \(\text{V}_\text{DD}\) is 1.1 V, the proposed PCDSA sensing error rate (SER) is close to 0% during normal sense operation, achieving a high sense speed of 123.6 ps and a low sense energy of 1.6533 fJ. Compared with the previously proposed TSC-PCDSA, the sense reliability is greatly improved, and the sense time and sense energy are reduced by 1.84 times and 1.27 times, respectively. Moreover, the proposed PCDSA can fully tolerate SEDU by optimizing the layout design. In the worst case where deposited charge \(Q_\text{inj}\) is 2 pC, it can achieve a shorter recover time of 1.28244 ns and a lower recover energy dissipation of 2.1604 pJ than the previously proposed TSC-PCDSA.

Since Internet of Things devices should ideally be self-powered, there is great demand for devices with ultra-low operating voltages that can run on energy harvested from a noisy environment. In this paper, a novel all spin logic (ASL) device with voltage controlled magnetic anisotropy (VCMA) effect amplified by negative capacitance (NC) is proposed for the first time. This novel device can operate at a working voltage as low as 1 mV. A three-step pulse scheme is also proposed. Based on simulations of the VCMA effect and the NC effect coupled with the spin modular approach, the feasibility of the proposed ASL device with a 1-mV working voltage and its immunity to variations in device parameters and supply voltage are analyzed.

True Random Number Generator(TRNG) is the key component for stochastic computation. It can also act as the Probabilistic Bit(P-Bit) which is the core device for Ising Computer. In previous study, we have proposed a novel programmable TRNG based on Spin Torque Nano-Oscillator(STNO). With this TRNG constructed with STNO, a time division multiplexing Ising computer is designed to work under the Incremental Coupling Rule. However, the programmable TRNG is still lack of a corporeal hardware implementation. In this work, a SPICE model for STNO which can accurately describe the frequency, resistance as well as noise spectrum is provided first. And then, a compact optimized Schmitt trigger circuit with 14 nm FinFET technology is proposed to construct the programmable TRNG. Finally, the performance of the compact programmable TRNG circuit is evaluated and discussed.