This letter reports a temperature-dependent limit for the subthreshold swing in MOSFETs that deviates from the Boltzmann limit at deep-cryogenic temperatures. Below a critical temperature, the derived limit saturates to a value that is independent of temperature and proportional to the characteristic decay of a band tail. The proposed expression tends to the Boltzmann limit when the decay of the band tail tends to zero. Since the saturation is universally observed in different types of MOSFETs (regardless of dimension or semiconductor material), this suggests that an intrinsic mechanism is responsible for the band tail.

This paper presents an experimental investigation, compact modeling, and low-temperature physics-based modeling of a commercial 28-nm bulk CMOS technology operating at cryogenic temperatures. The physical and technological parameters are extracted at 300, 77, and 4.2 K from dc measurements made on various geometries. The simplified-EKV compact model is used to accurately capture the dc characteristics of this technology down to 4.2 K and to demonstrate the impact of cryogenic temperatures on the essential analog figures-of-merit. A new body-partitioning methodology is then introduced to obtain a set of analytical expressions for the electrostatic profile and the freeze-out layer thickness in field-effect transistors operating from deep-depletion to inversion. The proposed physics-based model relies on the drift-diffusion transport mechanism to obtain the drain current and subthreshold swing, and is validated with the experimental results. This model explains the degradation in subthreshold swing at deep-cryogenic temperatures by the temperature-dependent occupation of interface charge traps. This leads to a degradation of the theoretical limit of the subthreshold swing at deep-cryogenic temperatures.

This article presents a physical model of the threshold voltage in MOSFETs valid down to 4.2 K. Interface traps close to the band edge modify the saturating temperature behavior of the threshold voltage observed in cryogenic measurements. Dopant freezeout, bandgap widening, and uniformly distributed traps in the bandgap do not change the qualitative behavior of the threshold voltage over temperature. Care should be taken because dopant freezeout results in a different physical definition of the threshold voltage. Using different definitions changes significantly the threshold current level. The proposed model is experimentally validated with measurements in large-area nMOS and pMOS devices of a commercial 28-nm bulk CMOS process down to 4.2 K. Our modeling results suggest that a pMOS-specific phenomenon in the gate stack is responsible for the non-saturating temperature behavior of the threshold voltage in pMOS devices.

This letter reports for the first time a full experimental study of performance boosting of tunnel FETs (TFETs) and MOSFETs by negative capacitance (NC) effect. We discuss the importance of capacitance matching between a ferroelectric NC and a device capacitance to achieve hysteretic and non-hysteretic characteristics. PZT ferroelectric capacitors are connected to the gate of three terminals TFETs and MOSFETs and partial or full matching NC conditions for amplification and stability are obtained. First, we demonstrate the characteristics of hysteretic and non-hysteretic NC-TFETs. The main performance boosting is obtained for the non-hysteretic NC-TFET, where the ON-current is increased by a factor of 500 times, transconductance is enhanced by three orders of magnitude, and the low slope region is extended. The boosting of performance is moderate in the hysteretic NC-TFET. Second, we investigate the impact of the same NC booster on MOSFETs. Subthreshold swing as steep as 4 mV/decade with a 1.5-V hysteresis is obtained on a commercial device fabricated in 28-nm CMOS technology. Moreover, we demonstrate a non-hysteretic NC-MOSFET with a full matching of capacitances and a reduced subthreshold swing down to 20 mV/decade.

In this article, we propose an explicit and analytic charge-based model for estimating short-channel effects (SCEs) in GaN high-electron-mobility transistor (HEMT) devices. The proposed model is derived from the physical charge-based core of the École Polytechnique Fédérale de Lausanne (EPFL) HEMT model, which treats HEMT as a generalized MOSFET. The main emphasis of this article is to estimate SCEs by effectively capturing 2-D channel potential distribution to calculate the reduced barrier height, drain-induced barrier lowering (DIBL), velocity saturation, and channel length modulation (CLM). The model is validated with TCAD simulation results and agreed with measurement data in all regions of operation. This represents the main step toward the design of high-frequency and ultralow-noise HEMT devices using AlGaN/GaN heterostructures.