This article presents a physical model of the threshold voltage in MOSFETs valid down to 4.2 K. Interface traps close to the band edge modify the saturating temperature behavior of the threshold voltage observed in cryogenic measurements. Dopant freezeout, bandgap widening, and uniformly distributed traps in the bandgap do not change the qualitative behavior of the threshold voltage over temperature. Care should be taken because dopant freezeout results in a different physical definition of the threshold voltage. Using different definitions changes significantly the threshold current level. The proposed model is experimentally validated with measurements in large-area nMOS and pMOS devices of a commercial 28-nm bulk CMOS process down to 4.2 K. Our modeling results suggest that a pMOS-specific phenomenon in the gate stack is responsible for the non-saturating temperature behavior of the threshold voltage in pMOS devices.

In this paper, we show how 5.5 tracks standard cells can be enabled at gate pitch 42 nm and metal pitch 21 nm and achieve 60% active power reduction from the 7nm node. A device downselection methodology driven by power and performance targets is introduced. This method demonstrates that three stacked nanosheets of 20 nm width are competitive with FinFETs made with two fins while relaxing the constraints on layout design rules.

The continued physical feature size scaling of CMOS transistors is experiencing asperities due to several factors (physical, technological, and economical), and it is expected to reach its boundary in the coming years. Sequential-3D (S3D) integration has been perceived as a promising alternative to continue the benefits offered by semiconductor scaling. This paper addresses the different variants of S3D integration and potential challenges to achieve a realizable solution. We analyze and quantify the benefits observed due to sequential scaling at a die level.

For the first time, an experimental assessment of the intradie mismatch properties of a FinFET technology is presented. By applying the analysis to different combinations of gate stack materials, it is shown that the best results are obtained with undoped fins, with matching performances on par or even superior to those of planar MOSFETs. Furthermore, the observation in the narrowest transistors of a noticeable degradation of the mismatch in both the threshold voltage and current factor points to line-edge roughness effects as the presumed key factor influencing intradie mismatch in the smallest fin geometries