The present paper focuses on various aspects regarding Hall Effect sensors’ design, integration, and behavior analysis. In order to assess their performance, different Hall Effect geometries were tested for Hall voltage, sensitivity, offset, and temperature drift. The residual offset was measured both with an automated measurement setup and by manual switching of the individual phases. To predict Hall sensors performance prior to integration, three-dimensional physical simulations were performed.

Five different Hall Effect sensors were modeled and their performance evaluated using a three dimensional simulator. The physical structure of the implemented sensors reproduces a certain technological fabrication process. Hall voltage, absolute, current-related, voltage-related and power-related sensitivities were obtained for each sensor. The effect of artificial offset was also investigated for cross-like structures. The simulation procedure guides the designer in choosing the Hall cell optimum shape, dimensions and device polarization conditions that would allow the highest performance.

Voltage Regulator Modules are DC-DC converters that power modern microprocessors. They must exhibit a fast dynamic response, in order to achieve satisfactory regulation performance in spite of the rapid load current variations. The pulse width modulator is one of the elements that determine the converter transient response. This work introduces a dual-edge modulator that outperforms conventional modulation schemes in terms of both small- and large-signal dynamic performances: first, its small-signal transfer function exhibits a phase boost action in the high-frequency range, enabling the design of robust, wide-bandwidth control loops. Furthermore, it introduces a reduced expected delay in response to a large-signal perturbation. The modulator transfer function is derived in this letter using the describing function approach, and it is validated by comparing its predictions to SIMPLIS simulations and to the measured loop transfer function of a synchronous buck converter, designed in a 130 nm CMOS technology.

This paper presents an extended model for transient and ac circuit-level simulation of minority carriers propagation through the substrate of smart power integrated circuits (ICs). A p-n junction and a diffusion resistor with capacitive components are proposed to efficiently simulate transient parasitic coupled currents in high-power stages. From a general chip layout, an equivalent substrate network including capacitive effects (junction and diffusion capacitances) can be extracted and parasitic bipolar transistor can be simulated for the first time in transient operation by circuit simulators once the minority carriers continuity conditions are satisfied. This paper shows simulation results of the implemented models in good agreement with those obtained from technology computer-aided design. This implies that transient layout dependent mechanisms between high-voltage aggressor wells and low-voltage victims can be verified in early stages of IC design flow.