The present paper focuses on various aspects regarding Hall Effect sensors’ design, integration, and behavior analysis. In order to assess their performance, different Hall Effect geometries were tested for Hall voltage, sensitivity, offset, and temperature drift. The residual offset was measured both with an automated measurement setup and by manual switching of the individual phases. To predict Hall sensors performance prior to integration, three-dimensional physical simulations were performed.

This paper presents a design-oriented charge-based model for dc operation of AlGaAs/GaAs and AlGaN/GaN-based high-mobility field-effect transistors. The intrinsic model is physics-based and does not introduce any empirical parameter. The central concept is based on the linear approximation of the channel charge density with respect to the surface potential, leading to explicit and continuous expressions for charges and current in all the regions of operation, including subthreshold. In addition, an effective circuit design methodology based on the pinchoff surface potential, the pinchoff voltage and the key concept of inversion coefficient (IC) is proposed, likewise for silicon MOSFET circuits.

In this article, an analytical predictive model of the negative capacitance (NC) effect in symmetric long channel double-gate junctionless transistor is proposed based on a charge-based model. In particular, we have investigated the effect of the thickness of the ferroelectric on the I-V characteristics. Importantly, our model predicts that the negative capacitance minimizes short channel effects and enhances current overdrive, enabling both low power operation and more efficient transistor size scaling, while the effect on reducing subthreshold slope shows systematic improvement, with subthermionic subthreshold slope values at high current levels. Our predictive results in a long channel junctionless with NC show an improvement in ON current by a factor of 6 in comparison to junctionless FET. The set of equations can be used as a basis to explore how such a technology booster and its scaling will impact the main figures of merit of the device in terms of power performances and gives a clear understanding of the device physics. The validity of the analytical model is confirmed by extensive comparisons with numerical TCAD simulations in all regions of operation, from deep depletion to accumulation and from linear to saturation.

In this paper, we investigate the technological constrains and design limitations of ultrathin body junctionless double gate MOSFET (JL DG MOSFET). Relationships between the silicon thickness and the doping concentration compatible with design requirements in terms of OFF-state-current and voltages are obtained and validated with TCAD simulations. This set of analytical expressions can be used as a guideline for technology optimization of JL DG MOSFETs.

Five different Hall Effect sensors were modeled and their performance evaluated using a three dimensional simulator. The physical structure of the implemented sensors reproduces a certain technological fabrication process. Hall voltage, absolute, current-related, voltage-related and power-related sensitivities were obtained for each sensor. The effect of artificial offset was also investigated for cross-like structures. The simulation procedure guides the designer in choosing the Hall cell optimum shape, dimensions and device polarization conditions that would allow the highest performance.