The dead-time elimination pulse width modulation (PWM) enables the drive pulses of the upper and the lower switching devices to alternate according to the current polarity, thus abandoning the dead-time and essentially avoiding the dead-time effect in power converters. However, the current zero-crossing will be distorted by the current jump generated by the drive-pulse alternation. And the current zero-crossing distortion will be further intensified if errors exist in the detected current polarity. Thanks to the noise-attenuation and frequency-adaptability characteristics of the double second-order generalized integrator frequency-locked loop (DSOGI-FLL), it can obtain accurate current polarities even in harmonic and unbalanced conditions. A DSOGI-FLL-based dead-time elimination PWM is therefore proposed in this paper, and several improvements are made to minimize the current zero-crossing distortion. An underlap period is added when alternating the upper and lower drive pluses to smooth the current jump at zero-crossing. And a delay compensation term is inserted in the DSOGI-FLL to compensate both the current measurement delay and the control delay. The effectiveness of the proposed DSOGI-FLL-based dead-time elimination PWM has been validated by experiments respectively in the unbalanced-current, power-change, and frequency-variation conditions with a RL load, as well as in a grid-connected converter.

A Neutral Point Clamped (NPC) type three-level inverter has the advantages of a low switch voltage and a high-quality output waveform. However, there are inherent problems, such as neutral point potential asymmetry and common mode interferences, which easily affect the symmetry of the three-phase output voltage and the safe operation of the inverter. Firstly, according to the different modulation degrees, the fluctuation of midpoint potential can be suppressed by adding an action time correction factor to the traditional space vector pulse-width (SVPWM) modulation strategy and virtual space vector pulse-width (VSVPWM) modulation strategy, respectively. Secondly, considering the suppression of common mode voltage, a new virtual space vector pulse-width (NVSVPWM) modulation strategy is proposed, which uses a set of new vector synthesis methods. Finally, the simulation and experiment prove that the NVSVPWM strategy with an action time correction factor can suppress the fluctuation of the neutral point potential and common mode voltage at the same time, and the effect is significant.

DC circuit breaker (DCCB) systems with a DC reactor in series are normally equipped in the voltage-sourced-converter-based multi-terminal DC (VSC–MTDC) systems for DC fault clearance. However, it is revealed that the use of DC reactors could undermine the system damping and deteriorate the system stability. In this paper, a controller based on hybrid sensitivity is proposed to improve the stability of power system and realize the power symmetry of multi-terminal systems. Firstly, based on a generalized MTDC small-signal model, an eigenvalue analysis is performed to provide deep insight into the stability issue imposed by DC reactors. Furthermore, a local controller based on hybrid sensitivity was proposed, and on this basis, a global controller was designed to solve asymmetrical power flow. Finally, a four-terminal VSC–MTDC model was built in Simulink to evaluate the performance of DC-PSS. Simulation results verify the effectiveness of the proposed controller in stabilizing MTDC systems and symmetrizing of power flow.