The dead-time elimination pulse width modulation (PWM) enables the drive pulses of the upper and the lower switching devices to alternate according to the current polarity, thus abandoning the dead-time and essentially avoiding the dead-time effect in power converters. However, the current zero-crossing will be distorted by the current jump generated by the drive-pulse alternation. And the current zero-crossing distortion will be further intensified if errors exist in the detected current polarity. Thanks to the noise-attenuation and frequency-adaptability characteristics of the double second-order generalized integrator frequency-locked loop (DSOGI-FLL), it can obtain accurate current polarities even in harmonic and unbalanced conditions. A DSOGI-FLL-based dead-time elimination PWM is therefore proposed in this paper, and several improvements are made to minimize the current zero-crossing distortion. An underlap period is added when alternating the upper and lower drive pluses to smooth the current jump at zero-crossing. And a delay compensation term is inserted in the DSOGI-FLL to compensate both the current measurement delay and the control delay. The effectiveness of the proposed DSOGI-FLL-based dead-time elimination PWM has been validated by experiments respectively in the unbalanced-current, power-change, and frequency-variation conditions with a RL load, as well as in a grid-connected converter.

Given the high complexity of the conventional three-level space-vector pulse-width-modulation (3L SVPWM), simplified SVPWM algorithms are usually adopted instead. However, existing simplifications for 3L SVPWM still have a large computation burden, which limits its applications, e.g., in high-switching-frequency silicon-carbide (SiC) converters with a short computation period. In this letter, based on a typical simplified algorithm known as the center-aligned 3L SVPWM, a simplified analytical algorithm in abc coordinate is proposed. The reference-voltage-vector adjustment and the calculation of modulation waves are unified based on the center-aligned SVPWM. The modulation waves can be analytically derived by only 8 simple equations, without sector determination, calculation and assignment of dwell times. Consequently, the complexity of implementing the 3L SVPWM is significantly reduced.

When faced with unbalanced dc-link voltages of three-level inverters, extra harmonics will be generated with reduced linear modulation region if the conventional pulsewidth modulation (PWM) for balanced dc-link voltages is adopted. In this article, in order to suppress output harmonics and maximize the linear modulation region, as well as to reduce switching losses, the discontinuous space-vector PWM (DSVPWM) is investigated and improved for three-level inverters with unbalanced dc-link voltages. First, subsectors in the vector diagram with unbalanced dc-link voltages are optimally redivided for low switching losses, and concisely determined by a cutting-line method. Then, the modulation waves are analytically derived based on the calculated dwell times of the vector states. And an analytical DSVPWM for dealing with unbalanced dc-link voltages is proposed and implemented by a carrier-based algorithm, which can significantly reduce the computation burden. Finally, the proposed analytical DSVPWM is verified through comparative experiments, presenting its merits of high linear modulation region, high efficiency, and relatively low output harmonics.

The symmetrical space vector pulsewidth modulation (SVPWM) has been widely adopted in three-level (3L) T-type inverters due to its low current harmonics and high linear modulation index. However, when faced with unbalanced and oscillated neutral-point (NP) voltages, extra current harmonics will be generated. In this article, a new solution is provided. Other than adopting the existing strategies for balancing the NP voltage, the symmetrical 3L SVPWM is optimized to work with unbalanced and oscillated NP voltages. First, the vectors are idealized, based on which ideal dwell times are obtained by an analytically simplified symmetrical 3L SVPWM. Then, a dc-zero-sequence component is calculated and injected to maximize the linear modulation index, and the real dwell times are further derived after the adjustment according to the “volt–second balance” principle. In addition, a control strategy is investigated to actively adjust the NP voltage. Finally, the optimized symmetrical 3L SVPWM is verified by comparative experiments, showing its low current harmonics with unbalanced and oscillated NP voltages.

The low-voltage ride-through (LVRT) capability of the doubly-fed induction generator (DFIG) based on the conventional excitation converter is insufficient under severe grid faults. The reason is that the dynamic rotor electromotive forces (EMF) will far exceed the dc-link voltage. To solve this issue, this letter proposes an enhanced excitation converter with parallel/series dc-link based on the triple active bridge (TAB) for DFIG. The dc-link of the enhanced excitation converter consists of the TAB and switching circuit, replacing the capacitive-type dc-link. Based on this topology, the dc-link voltage can increase instantaneously during severe grid faults to resist rotor EMF and improve the LVRT capability of DFIG. Compared with existing LVRT schemes, the enhanced excitation converter enables DFIG to achieve LVRT and inject the reactive current requirements of the grid code into the grid under severe grid faults. Finally, experiments verified the effectiveness of the proposed enhanced excitation converter and its control strategy.

Multiple second-order generalized integrators (MSOGI) has been widely used to extract the signal that contains multiple harmonics. The MSOGI needs to be implemented in the discrete-time domain for its practical applications. More critically, the discretization method can greatly affect its performance. The existing discretization methods for MSOGI can be divided into three categories: entire transfer-function discretization, SOGI-transfer-function discretization, and integrator discretization. The theoretical analysis indicates that the first method can avoid the errors caused by unit delay, but it is hard to be digitally realized for high-order transfer functions. The other two methods have nonnegligible errors in both the phase and the quadrature characteristic due to the unit delay. In this letter, we propose a novel discretization method by modifying the structure of integrator discretization. This method can enhance the performance in both the phase and the quadrature characteristic with an acceptable computation burden, which has been theoretically analyzed and experimentally verified.