This paper presents a frequency-splitting-based wireless power and data transfer IC that simultaneously delivers power and forward data over a single inductive link. For data transmission, frequency-shift keying (FSK) is utilized because the FSK modulation scheme supports continuous wireless power transmission without disruption of the carrier amplitude. Moreover, the link that manifests the frequency-splitting characteristic due to a close distance between coupled coils provides wide bandwidth for data delivery without degrading the quality factors of the coils. It results in large power delivery, high data rate, and high power transfer efficiency. The presented IC fabricated in a 180-nm BCD process simultaneously achieves up-to-115-mW wireless power delivery to the load and 2.5-Mb/s downlink data rate over the single inductive link. The measured overall power efficiency from the DC power supply at the transmitter module to the load at the receiver module reaches 56.7$\%$ at its maximum, and the bit error rate is lower than 10$^{-6}$ at 2.5 Mb/s. As a result, the figure of merit (FoM) for data transmission is enhanced by 2 times, and the FoM for power delivery is improved by 38.7 times compared to prior state-of-the-arts using a single inductive link.

This article presents a fully integrated multi-phase (MP) buck converter for on-chip power management units A peak-and-valley differential sensing (PVDS) scheme based on a flying capacitor is proposed to evenly balance the multiple inductor currents without significant power overhead even under mismatches in inductances, parasitic series resistances, and control-signal skews among phases. In addition, dynamic re-allocation of on-chip capacitors enables an even more optimal frequency response and output ripple based on the number of activated phases. It also improves the chip area efficiency, resulting in a higher power density. The proposed DLL-based MP clock generation provides high granularity in the phase-shedding control to achieve high efficiency over a wide load range. The proposed fully integrated buck converter using six bond-wire inductors (1 nH) was fabricated in a 28-nm CMOS process. The chip running at a frequency of 400 MHz/phase can finely adjust the number of active phases by an integer step ranging from 1 to 6 through sensing a load current. A maximum power density of 1.23 W/mm $^{2}$ and a peak efficiency of 83.7% were measured. This work achieved an ultra-fast dynamic voltage scaling (DVS) rate of 75 mV/ns.

For fast buffering of large stepwise input to an nF-range capacitive load, this article presents a 5-V rail-to-rail (RTR) input–output paralleled-amplifier (PA) in which a dynamic class-C amplifier (DCCA) and a linear single-stage operational transconductance amplifier (OTA) are combined in parallel. During slew time, the DCCA, which is designed to consume a near-zero static current, dominantly supplies the dynamic current up to 8.5 mA to the output. When the output gets closer to the fine-settling region, the DCCA is rapidly faded out in virtue of a dedicated near-zero dead-zone control (NDZC), and it hands over to the linear OTA. A current-redistributive RTR $G_{\text {m}}$ -boosting technique is also proposed so that the OTA can have a wide gain-bandwidth product (GBW) even over the RTR input range while minimizing the quiescent current dissipation. The prototype chip was fabricated only with 0.5- $\mu \text{m}$ 5-V CMOS devices, and it occupies a die area of 0.03 $\mu \text{m}^{2}$ . The proposed amplifier consumed a static current of 3.1 $\mu \text{A}$ with a supply voltage of 5 V. The slew rates (SRs) with load capacitances ( $C_{\mathrm {L}}$ ) of 0.8 and 10 nF were measured to be 10.3 and 0.86 V/ $\mu \text{s}$ , respectively, for a step input of $\Delta $ 4.2 V, which is a state-of-the-art result compared to prior chips. The measured GBW of 10–127 kHz was achieved over 0.8–10 nF $C_{\mathrm {L}}$ with ≥ 59° phase margin (PM). The measured GBW deviation in a common-mode voltage ( $V_{\mathrm {CM}}$ ) range of 0.3–4.7 V was within the maximum of 20%.

To achieve commercial scalability, fiber-based quantum key distribution (QKD) systems must be integrated into existing optical communication infrastructures, rather than deployed exclusively on dedicated dark fibers. Integrating QKD into optical access networks (OANs) would be particularly advantageous, as these networks provide direct connectivity to end users for whom security is critical. Such integration can address the inherent security vulnerabilities in current OANs, which are primarily based on time-division multiplexing passive optical networks (TDM-PONs). However, integrating QKD into PONs poses significant challenges due to Raman noise and other detrimental effects induced by PON signals, which intensify as the launched power of PONs increases to support higher transmission speeds. In this study, we review recent advancements in both QKD and access network technologies, evaluate the technical feasibility of QKD-OAN integration, and propose cost-effective strategies to facilitate the widespread deployment of QKD in future access networks.

Constant on-time (COT) buck converters offer fast transient responses and a simple architecture but face challenges like switching frequency variation, instability with low-equivalent series resistance (ESR) capacitors, and DC output voltage offset. This paper reviews advanced COT control techniques developed to overcome these limitations. We examine methods for frequency stabilization (e.g., adaptive on-time, phase-locked loop), stability with low-ESR capacitors (e.g., passive and active ripple injection, virtual inductor current), and improved DC regulation (e.g., offset cancellation). This review also covers techniques for optimizing transient response and multiphase architectures for high-current applications.

This paper presents a 5-bit VCO-based neural recording IC, which directly quantizes the input signal and achieves a large dynamic range (DR) to process the small-amplitude neural signal in the presence of the large-amplitude stimulation artifact (SA). A feedback-controlled source degeneration is applied to the input transconductor circuit (Gm,in) by using a resistor DAC (R-DAC). It mitigates the circuit nonlinearity, resulting in a large signal-to-noise-and-distortion ratio (SNDR) and a high input impedance (Z _in ). The implemented neural recording IC achieves 813dB SNDR over 200Hz signal bandwidth and 200mV _PP maximum allowable input range while consuming 3.9μW per channel.