Recently, there has been an increasing demand for SoCs in the biomedical field. In implantable applications, SoCs are designed under very stringent power and area constraints. The analog and mixed-signal circuits as well as digital circuits in those SoCs require a clock source, because clock-based signal-processing techniques, such as sampling and chopper stabilization, are often used. The primary clock source for such SoCs needs to provide good accuracy and long-term stability of the oscillation frequency foscto minimize variations and drifts of the system characteristics. A fairly pure clock signal is required to avoid signal distortion when sampling or chopping techniques are applied. Considering such a source is typically a free-running oscillator, and biomedical signals of typical interest reside at low frequencies, the close-in phase noise is important. For implantable biomedical sensor SoCs, due to high power consumption of quartz crystal oscillators and their bulky size, monolithic oscillators are preferred as a primary clock source. Relaxation oscillators can operate with low power and set their oscillation period Tosc in well-defined manner while consuming small silicon area. However, their performance is limited by process variations, noisy current sources, and noise and offset voltages of the comparators. Geraedts et al. presented an idea of subtracting a fixed charge packet and filtering out the comparator noise to improve the phase noise particularly at large offset frequencies. In this work, a self-clocked offset-cancellation scheme is presented for comparators in the relaxation oscillator, resulting in smaller frequency drifts and lower close-in phase fluctuations, which are more relevant parameters for primary clock sources in implantable biomedical SoCs.

This paper presents a frequency-splitting-based wireless power and data transfer IC that simultaneously delivers power and forward data over a single inductive link. For data transmission, frequency-shift keying (FSK) is utilized because the FSK modulation scheme supports continuous wireless power transmission without disruption of the carrier amplitude. Moreover, the link that manifests the frequency-splitting characteristic due to a close distance between coupled coils provides wide bandwidth for data delivery without degrading the quality factors of the coils. It results in large power delivery, high data rate, and high power transfer efficiency. The presented IC fabricated in a 180-nm BCD process simultaneously achieves up-to-115-mW wireless power delivery to the load and 2.5-Mb/s downlink data rate over the single inductive link. The measured overall power efficiency from the DC power supply at the transmitter module to the load at the receiver module reaches 56.7$\%$ at its maximum, and the bit error rate is lower than 10$^{-6}$ at 2.5 Mb/s. As a result, the figure of merit (FoM) for data transmission is enhanced by 2 times, and the FoM for power delivery is improved by 38.7 times compared to prior state-of-the-arts using a single inductive link.

This article presents an ultra-low-noise differential relaxation oscillator that achieves a phase noise figure of merits (FoMs) of 157.7 and 162.1 dBc/Hz, respectively, at 1- and 100-kHz frequency offsets. The oscillator is inherently robust against 1/f noise, while swing-boosting minimizes the phase noise arising out of thermal noise. Furthermore, an inverter-based differential comparator maximizes power efficiency, enabling FoMs close to the fundamental limits. Operating at 10.5 MHz and consuming 219.8 μW from a 1.4-V supply, the oscillator achieves a period jitter of 9.86 psrms, equivalent to a relative jitter of 0.01%. The oscillator occupies an active area of 0.015 mm² in a 0.18-μm standard CMOS process.

We present a fully implantable neural recording IC with a spike-driven data compression scheme to improve the power efficiency and preserve crucial data for monitoring brain activities. A difference between two consecutive neural signals, Δ-neural signal, is sampled in each channel to reduce the full dynamic range and the required resolution of an analog-to-digital converter (ADC), enabling the whole analog chain to be operated at a 0.5-V supply. A set of multiple Δ-signals are stored in analog memory to extract the magnitude and frequency features of the incoming neural signals, which are utilized to discriminate spikes in these signals instantaneously after the acquisition in the analog domain. The energy- and area-efficient successive approximation ADC is implemented and only converts detected spikes, decreasing the power dissipation and the amount of neural data. A prototype 16-channel neural interface IC was fabricated using a 0.18-μm CMOS process, and each component in the analog front-end was fully characterized. We successfully demonstrated precise spike detection through both in vitro and in vivo acquisition of the neural signal. The prototype chip consumed 0.88 μW/channel at a 0.5-V supply for the recording and compressed about 89% of neural data, saving the power consumption and bandwidth in the system.

Skyrmion-based devices are an attractive candidate for nonvolatile memory and low-power computation. In a real device, however, skyrmions easily annihilate at device edges, which hampers device applications. Here, we present a novel skyrmion-based logic device, which takes advantage of the skyrmion annihilation (SA) and increases the efficiency of logic operation. An SA half adder (HA) is implemented in a ferromagnet/heavy metal nanotrack by introducing a geometric notch that annihilates the skyrmion. In addition, full adder and n-bit SA ripple-carry adder are demonstrated by directly cascading the SA HAs. The prototype of a 32-bit SA ripple-carry adder consumes energy as low as 0.62 pJ per each operation, which is only 18% of the previously proposed skyrmion adder. Our SA logic gate can, therefore, be a promising candidate for the beyond-CMOS logic device.

This paper reviews architectures and circuit implementations of on-chip sinusoidal signal generators (SSGs) for electrical impedance spectroscopy (EIS) applications. In recent years, there have been increasing interests in on-chip EIS systems, which measure a target material’s impedance spectrum over a frequency range. The on-chip implementation allows EIS systems to have low power and small form factor, enabling various biomedical applications. One of the key building blocks of on-chip EIS systems is on-chip SSG, which determines the frequency range and the analysis precision of the whole EIS system. On-chip SSGs are generally required to have high linearity, wide frequency range, and high power and area efficiency. They are typically composed of three stages in general: waveform generation, linearity enhancement, and current injection. First, a sinusoidal waveform should be generated in SSGs. The generated waveform’s frequency should be accurately adjustable over a wide range. The firstly generated waveform may not be perfectly linear, including unwanted harmonics. In the following linearity-enhancement step, these harmonics are attenuated by using filters typically. As the linearity of the waveform is improved, the precision of the EIS system gets ensured. Lastly, the filtered voltage waveform is now converted to a current by a current driver. Then, the current sinusoidal signal is injected into the target impedance. This review discusses the principles, advantages, and disadvantages of various techniques applied to each step in state-of-the-art on-chip SSGs. In addition, state-of-the-art designs are compared and summarized.