This article presents a neural-recording IC with automatic gain control (AGC) according to the input signal level. AGC enhances the dynamic range (DR) of the recording IC by more than 30 dB and allows it to take the benefits of the front-end amplification-based and direct-conversion-based recording structures concurrently. By adaptively controlling the analog front-end (AFE) gain, the input-referred noise (IRN) of the overall system is greatly reduced while ensuring a wide DR. A continuous-time (CT) dynamic-zoom $\Delta \Sigma $ ADC (CT-Zoom-ADC) is used for power-efficient two-step conversion. The coarse conversion output is reused for AGC, and the fine conversion resolution is adjusted adaptively by modifying the oversampling ratio according to the varying AFE gain. The presented neural-recording IC achieves 99.5-dB DR and 6.1- $\mu \text{V}_{\textrm {rms}}$ IRN over 5-kHz bandwidth, resulting in FoM _DR of 185.2 dB, the effective number of bits (ENOB) of 11.4 bits, and tolerance against artifacts with differential voltage amplitudes up to 1.6 $\text{V}_{\text {pp}}$ . Measurements with pulsatile artifacts and experiments in vivo validate that the proposed IC is applicable to the closed-loop neural interface.

This article presents a single-mode dual-path buck-boost converter (SDBBC) for mobile devices powered by lithium-ion batteries. Unlike the conventional buck-boost converter (CBBC), this SDBBC conducts buck and boost operations using a hybrid structure with two flying capacitors ( $C_{F1}$ , $C_{F2}$ ) and one inductor. This hybrid structure eliminates any mode transition between circuit configurations, covering both the buck and boost operations continuously within a single-mode operation. By consistently connecting the inductor to the load with a secondary path formed by $C_{F1}$ and $C_{F2}$ , the average of the inductor current ( $I_{L}$ ) is always smaller than the load current ( $I_{\mathrm {LOAD}}$ ) across all the output voltage conversion ratios, thus incurring low conduction loss and switch transition loss. Also, the current delivered to the load increases as the duty ratio increases, so the right half-plane (RHP) zero is removed. Therefore, the proposed SDBBC achieves high power efficiency seamlessly across the whole conversion range, 94.8% peak efficiency is achieved even with an inductor of 175 $\text{m}\Omega $ dc resistance (DCR), and 95.58% efficiency is achieved in the boost operation at a heavy load current of 1 A using a large size inductor with 19 $\text{m}\Omega $ DCR.

This paper presents a PVT-robust error-feedback (EF) noise-shaping SAR (NS-SAR) ADC for direct neural-signal recording. For closed-loop bidirectional neural interfaces enabling the next generation neurological devices, a wide-dynamic-range neural recording circuit is required to accommodate stimulation artifacts. A recording structure using an NS-SAR ADC can be a good candidate because the high resolution and wide dynamic range can be obtained with a low oversampling ratio and power consumption. However, NS-SAR ADCs require an additional gain stage to obtain a well-shaped noise transfer function (NTF), and a dynamic amplifier is often used as the gain stage to minimize power overhead at the cost of vulnerability to PVT variations. To overcome this limitation, the proposed work reutilizes the capacitive-feedback amplifier, which is the analog front-end of the neural recording circuit, as a PVT-robust gain stage to achieve a reliable NS performance. In addition, a new chopper-based implementation of a passive high-pass IIR filter is proposed, achieving an improved NTF compared to prior EF NS-SAR ADCs. Fabricated in a 180-nm CMOS process, the proposed NS-SAR ADC consumes 4.3-μW power and achieves a signal-to-noise-and-distortion ratio (SNDR) of 71.7 dB and 82.7 dB for a bandwidth of 5 kHz and 300 Hz, resulting in a Schreier figure of merit (FOM) of 162.4 dB and 162.1 dB, respectively. Direct neural recording using the proposed NS-SAR ADC is demonstrated successfully in vivo , and also its tolerance against stimulation artifacts is validated in vitro .

This work presents a 4 kb 8T-SRAM computation-in-memory (CIM) macro based on hybrid computation using digital in-memory-array computing (DIMAC) and phase-domain near-memory-array computing (PNMAC). By employing multiple local dual-column arrays (LDCAs), bit-wise multiplications are computed digitally in memory with high energy efficiency and throughput. The PNMAC performs the summation and accumulation in parallel with a high dynamic range by using a proposed steering-DAC-based differential current-controlled-oscillator (DCCO). After the phase-domain accumulation is completed, only a one-time digital conversion needs to be performed using a phase quantizer with negligible phase-to-digital conversion overhead. Moreover, by effectively reusing the steered current to accumulate the multiplication results fed from the DIMAC, the power consumption of the PNMAC can be greatly reduced. The macro fabricated in a 65 nm process achieves 22.4TOPS/W peak energy efficiency and $19.03~\mu \text{W}$ power consumption with a 59.8% zero-skipping rate, which is $96.05\times $ lower than state of the art.

The escalating demand for high-resolution sensor interface systems, driven by the proliferation of the Internet of Things (IoT) and wearable smart devices, has led to the widespread use of capacitive sensing transducers. These transducers are valued for their low-noise and low-power characteristics, making them suitable for various applications, including environmental and biomedical sensing. However, designing a high-resolution capacitive sensor interface system while maintaining power efficiency remains challenging. This article proposes a high-resolution energy-efficient highpass (HP) $\Delta\Sigma$ capacitance-to-digital converter (CDC) architecture. The architecture incorporates a 2 ${\textrm{nd}}$ -order HP $\Delta\Sigma$ modulator ( $\Delta\Sigma$ M) and a continuous-time capacitance-to-voltage converter (CT CVC). The proposed CDC achieves an excellent capacitance resolution of 5.85 aF $_\textrm{rms}$ , with a power efficiency of 46 fJ/conversion-step and an FoM $_\textrm{S}$ of 187.4 dB. The HP $\Delta\Sigma$ M, designed with superior power efficiency, offers a promising solution for high-resolution capacitive sensor applications. Compared to state-of-the-art, the proposed CDC achieves more than 2 $\times$ FoM $_\textrm{S}$ improvement while maintaining competitive FoM $_\textrm{W}$ .

Fast neural electrical impedance tomography (EIT) is a promising method to not only record neural activities but also to localize them in peripheral nerves in a minimally invasive way. A much higher image frame rate is required for this application than conventional impedance measurement applications, which generally adopt the I/Q demodulation technique. To achieve a high enough frame rate to capture neural activities along the peripheral nerve fascicle, this paper proposes synchronous sampling (SS) and fast baseline tracking based on successive approximation (SA). The SS method needs an injection of only a single or a few periods of square-wave current signal for the amplitude measurement by synchronously sampling the received voltage signal. The proposed SA-based baseline tracking provides fast signal recovery from unwanted motion artifacts or baseline drifts. The designed readout circuit uses a two-step conversion where its coarse bits are generated from a current-based baseline cancellation circuit and its fine bits from a following SAR ADC. Thanks to the baseline tracking based on the SS and SA, the proposed IC achieves a faster frame rate of 312 fps with continuous baseline update and 500 fps with constant baseline compared to state-of-the-art works. The implemented IC is validated by measuring a water-filled tank and reconstructing its tomographic image. The results show successful discrimination of varied impedance areas over the tank.