The study examines the impact of the COVID-19 pandemic on the digital competencies of teachers and the educational achievements of students, focusing on Serbia and comparisons with other countries. For this study, a survey was conducted in three phases, completed by teachers. The time periods during which the surveys were filled out are characteristic because they correspond to specific points in time (June 2019, June 2022, and May 2023). The aim of the first study, conducted in June 2019, was for every school in the Republic of Serbia to explore teachers’ digital competencies as a recommendation of the Ministry of Education. Later, this survey took on a different purpose with the onset of the pandemic. The pandemic exposed challenges such as insufficient teacher preparation for online teaching, educational inequalities affecting students from lower socio-economic backgrounds, and varying levels of adaptability among students. The hypothesis of this research is as follows: Teachers demonstrate a significantly higher level of digital literacy after the crisis caused by the COVID-19 virus than before the crisis. The findings reveal improvements in teachers’ digital skills after the crisis situation, particularly in hardware, software, and internet use, alongside a shift in the primary purpose of digital tools from entertainment to education. The study emphasizes the importance of continuous professional development, standardized e-learning devices, and improved digital infrastructure to enhance the quality of education. The research found that teachers in Serbia showed a significantly higher level of digital competencies after the crisis situation. Key recommendations include integrating digital skills into teacher training, fostering innovative pedagogical practices, and addressing the digital divide to ensure equitable access to education in the future.

A PLL or phase-locked loop is a control system that creates an output signal whose phase is related to the phase-locked loop and represents controlled input signal. The goal of this research is to first investigate the functioning of new PLL neural networks and then, in the research section, explore an approach involving the extraction of neural symmetrical voltage components. The architectural characteristics of phase-locked loops (PLLs) typically include capture and lock ranges, bandwidth, and transient response. The new neural PLL architecture offers several advantages, such as low noise performance, reduced silicon area, and compatibility with low supply voltages. However, it may also present disadvantages, including hardware dependency and potential design complexity compared to traditional PLL architectures. Evaluating these factors is crucial, depending on the specific needs of the application. In this paper, we present the scientific research included in the experimental part where we investigate the performance of the proposed neural PLL, for which experimental comparisons with the conventional PLL in a distorted reference frame are necessary. Structural columns or structural circles will be used for graphic display. The following research methods and techniques will be applied: instruments, basic methods and data processing procedures - if they are foreseen. What makes this work a scientific research work is a descriptive method that will be used. To better understand how PLLs work, we propose an original three-phase neural approach for components of the system’s phase and symmetry. The quality of the electricity can be assessed and managed with this framework. Our study shows that the full neural architecture may be applied to three-phase power systems because it is based on DSP supplies. Additionally, we present the performance of the PLL system in a three-phase power supply context. Different regulators, such as PI and RST based on phase logic, are incorporated into the PLL scheme. The results suggest that the neural PLL could make a significant contribution in applications where the quality and efficiency of three-phase power systems are essential.

The term “big data” was coined to describe the vast amounts of information science and technology data that have been generated on a large scale over time. Based on existing research, the current state of the problem was observed, i.e. “Poor internet speed, network downtime, constant traffic jams, energy consumption due to increasing internet connectivity, which increases management overhead costs, network unavailability”. Therefore, this research provides a brief overview of the list of bandwidth optimization models applied through previous research works, indicating the optimal algorithms that work with each of the models in formulating a new bandwidth optimization model that solves the mixed integer linear programming technique problem which was the approach adopted from the existing works. necessary for wireless networks. This paper aims to evaluate and analyze existing bandwidth optimization models, optimal algorithms with each model, as well as a new bandwidth optimization model that solves the problem of previous optimization techniques. In wireless networks, the most energy-consuming activities are network bandwidth transmission and reception. Energy consumption for data transmission or reception depends on the volume of network traffic and the speed of network traffic from source to destination.

Globalization of financial flows, monetary integration, deregulation and cutting-edge information technology promote the growth of efficient capital market, as an integral part of national financial markets. The aim of this paper is to point out advantages and disadvantages of the development of relatively new capital market in the transition period of the Serbian economy. In the broadest sense, financial market is an organized place, where supply and demand for financial asset meet, forming the price of financial asset. In short, financial market includes all the institutions and procedures by which sellers and buyers of financial instruments are connected regardless of the nature of financial instrument. It enables unhindered funds and capital flow to the place where it can be employed most efficiently. Financial market development, depth and stability are crucial for economic growth and they are also a significant indicator of national market development in relation to its environment.

Gene chips are widely used in animal and plant science. Generally, microarrays are of two types, cDNA or oligonucleotide, cDNA was developed at Stanford University, while oligonucleotides were developed by Affymetrix. We will explore genetic chips, the technology used for their production and reading, and their applications. Gene chips, which are becoming increasingly popular throughout the field of molecular biology and biotechnology, are a recently developed technique that provides efficient access to genetic information using miniaturized high-density arrays of DNA or oligonucleotide probes. Both fundamental and applied research benefit greatly from the specific advantages of this method. There are several steps in the design and implementation of DNA chip technology: probe generation, chip fabrication, sample preparation, analysis, readout, and software. At present, the main application of large-scale microarrays is comparative expression analysis. Microarray technology allows for the analysis of expression profiles for thousands of genes in parallel. One of the most significant applications of this technique is gene expression and profiling on a genome-wide scale. Genechip technology is a new technique that will undoubtedly significantly increase the speed of molecular biology research.

Aperiodic pseudo-random impulse (APPI) trains represent deterministic yet reproducible sequences that mimic the irregularity of natural processes. They allow complete control over inter-spike intervals (ISIs) and pulse widths (PWs). Such signals are increasingly relevant for low-probability-of-intercept (LPI) communications, radar testing, and biomedical applications, where controlled variability mitigates adaptation and enhances stimulation efficiency. This paper presents a modular APPI generator implemented on an Arduino Mega platform, featuring programmable statistical models for ISI (exponential distribution) and PW (uniform distribution), dual-timing mechanisms (baseline loop and Timer/ISR, clear-timer on compare (CTC)), a real-time telemetry and software interface, and a safe output chain with opto-isolation and current limitation. The generator provides both reproducibility and tunable stochastic dynamics. Experimental validation includes jitter analysis, Kolmogorov–Smirnov tests, Q–Q plots, spectral and autocorrelation analysis, and load integration using a constant-current source with compliance margins. The results demonstrate that the Timer/ISR (CTC) implementation achieves significantly reduced jitter compared to the baseline loop, while maintaining the statistical fidelity of ISI and PW distributions, broad spectral characteristics, and fast decorrelation. Experimental verification was extended across a wider parameter space (λ = 0.1–100 Hz, PW = 10 µs–100 ms, 10 repetitions per condition), confirming robustness and repeatability. Experimental validation confirmed accurate Poisson/Uniform ISI generation, sub-millisecond jitter stability in the timer-controlled mode, robustness across λ = 0.1–100 Hz and PW = 10 µs–100 ms, and preliminary compliance with isolation and leakage limits. The accompanying Python GUI provides real-time control, telemetry, and data-logging capabilities. This work establishes a reproducible, low-cost, and open-source framework for APPI generation, with direct applicability in laboratory and field environments.