A new high order sigma delta modulator called MSCL (multistage closed-loop) is presented. It uses a global feedback to lower the sensitivity to circuit imperfections and no digital prefiltering is required before summing the output of each stage. Stable modulators can be realised up to the sixth order. Simulation and experimental results will be presented.

A Nano quiescent current Power Management for Autonomous Wireless Sensor Network dedicated to indoor and outdoor Photovoltaic (PV) Energy Harvesting is presented. The standby current consumption is 130nA @ 2.4V The battery can be charged with less than 5% of the harvested energy from low light (70 lux) to high light (1 sun). The IP starts charging at light level as low as 10 lux providing ≃ 1μW. The voltage range is 2.4V-3.2V The system load can be powered up to 400mA. This power management is manufactured using the CMOS 90nm technology in a 0.4mm ² die area.

This paper presents a 14-bit Incremental Sigma-Delta \((\varSigma \varDelta) \) analog-to-digital converter suitable for column wise integration in a CMOS image sensor. A two step conversion is performed to improve the conversion speed. As the same \(\varSigma \varDelta \) modulator is used for both steps, the overall complexity is reduced. Furthermore, the use of inverter-based amplifiers instead of operational transconductance amplifier facilitates the integration within the column pitch and decreases power consumption. MonteCarlo simulations have been done in order to validate the design of the inverter. The proposed ADC is designed in \(0.18\,\upmu \hbox {m}\) CMOS technology. The simulation is performed with a 1.8 V voltage supply, a 20 MHz system clock frequency and an oversampling ratio (OSR) of 70, and achieves a power consumption is \(460 \, \upmu \hbox {W}\), a SNDR of 85.4 dB at a sampling rate of 250 kS/s.

The ST segment of an ECG signal is a feature that changes in the event of cardiac ischemia, a condition that is an early warning sign of myocardial infarction. Being able to monitor this feature in real time would be highly beneficial for preventing recurrent heart attacks. However, to be worn daily, such a monitoring device must be extremely miniaturized, down to the scale of a single integrated circuit. Currently, it is possible to integrate a heart rate detector, but, to our knowledge, no existing work presents a chip capable of detecting ST segment deviation. This is mainly because accurate ST segment measurement requires low-distortion signal processing, as specified in the International Electrotechnical Commission (IEC) standard. At the same time, the system is required to filter out baseline wander, whose frequency components may partially overlap with those of the ST segment. In this study, we relied on wavelet-based analysis and reconstruction to compare several wavelet types. We optimized their hyperparameters to minimize implementation complexity while satisfying the low-distortion constraints. We also propose an ASIC-oriented architecture and evaluate its post-layout performance in terms of area and power consumption. The post-layout results indicate that the Daubechies wavelet db3 offers the best trade-off among the evaluated configurations. It exhibits an area utilization of $1.18$ mm² and a post-layout power consumption of $4.89$ $\mathsf{\mu }$W, while preserving the ST segment in compliance with the IEC standard, thanks in particular to its effective baseline wandering filtering of $6.9$ dB. These results demonstrate the feasibility of embedding automatic ST segment extraction on-chip.

This article proposes a new integrated analog implementation of the Pan–Tompkins algorithm. This algorithm, generally implemented in the digital domain at the cost of higher power consumption, is one of the most efficient for QRS detection in electrocardiographic signals. This circuit has been designed for use on small mammals like rats for the study of pulmonary arterial hypertension. The specificities of the architecture proposed in this article are a sub-threshold-operated architecture to perform the amplification, noise filtering, and differentiation of the signal in a unique block to limit the power consumption; an analog squarer; and an analog monostable reshaping-circuit followed by a digital counter clocked by an ultra-low power relaxation oscillator. Compared with the state of the art, this circuit, designed with the X-FAB xh018 180 nm CMOS technology, presents one of the lowest power consumptions currently reported, at 28.5 nW, 76% of which is consumed in the current, voltage, and time references. Post-layout simulation results show a reliable 98.57% heart beat detection accuracy using the MIT-BIH arrhythmia database and 99.85% accuracy for healthy sinus rhythm electrocardiograms. The robustness of the circuit is also investigated, and mitigating solutions are proposed for each critical block.