The work presented here is related to Cyclope, an integrated active 3-D vision system. The challenge is to realize an integrated sensor which achieve real-time depth vision with constraints on size, consumption and computational resources. In this paper, we present acquisition method which allows to grab both texture and IR pattern images at least at 25 frames/s. The method uses a pulsed IR laser pattern projector and CMOS image sensor with programmable integration time. This sensor is realized in a standard CMOS technology and does not envolve any special optical filtering. We present some experimental results with the realization of a large scale demonstrator using a SOPC prototyping board and the said image sensor.

This paper presents a 14-bit Incremental Sigma-Delta \((\varSigma \varDelta) \) analog-to-digital converter suitable for column wise integration in a CMOS image sensor. A two step conversion is performed to improve the conversion speed. As the same \(\varSigma \varDelta \) modulator is used for both steps, the overall complexity is reduced. Furthermore, the use of inverter-based amplifiers instead of operational transconductance amplifier facilitates the integration within the column pitch and decreases power consumption. MonteCarlo simulations have been done in order to validate the design of the inverter. The proposed ADC is designed in \(0.18\,\upmu \hbox {m}\) CMOS technology. The simulation is performed with a 1.8 V voltage supply, a 20 MHz system clock frequency and an oversampling ratio (OSR) of 70, and achieves a power consumption is \(460 \, \upmu \hbox {W}\), a SNDR of 85.4 dB at a sampling rate of 250 kS/s.

The work presented here is related to Cyclope, an embedded active 3D vision system. The challenge is to realize an integrated sensor which achieve real-time depth vision with constraints on the size, consumption and computational resources. Cyclope is based on active vision and is integrated in a VSiP (visual system in package) allowing multiple technology cohabitation, such as a CMOS imager or an AsGa VSCEL, in the same chip size package. In this paper we present an acquisition method which allows to grab both texture and IR pattern images at a 25 image/s frame rate. The method uses a pulsed IR laser pattern projector and CMOS image sensor with programmable integration time. This sensor is realized in a standard silicon technology and without additional optical filtering. The first experimental results are presented to validate our approach with the realization of a functional prototype using a SOPC board, a structured pattern projector and the designed image sensor.

Recent advances in vision system integration allows to design new integrated sensors which are able to achieve complexes tasks. The 'Cyclope' project aims to develop a novel integrated sensor for real-time 3D reconstruction. It includes an active vision sensor, a digital centralized processing architecture and a communication block. This sensor is designed to obtain a monolithic integrate vision system. This paper presents the digital processing architecture which is a massively-parallel architecture in a totally scalable IP to assure the compatibility with application constraints. This architecture has been implemented on an FPGA circuit and we demonstrate, with accurate results, the realtime operations.

Much work has been dedicated to estimating and optimizing workloads in high-performance computing (HPC) and deep learning. However, researchers have typically relied on few metrics to assess the efficiency of those techniques. Most notably, the accuracy, the loss of the prediction, and the computational time with regard to GPUs or/and CPUs characteristics. It is rare to see figures for power consumption, partly due to the difficulty of obtaining accurate power readings. In this paper, we introduce a composite score that aims to characterize the trade-off between accuracy and power consumption measured during the inference of neural networks. For this purpose, we present a new open-source tool allowing researchers to consider more metrics: granular power consumption, but also RAM/CPU/GPU utilization, as well as storage, and network input/output (I/O). To our best knowledge, it is the first fit test for neural architectures on hardware architectures. This is made possible thanks to reproducible power efficiency measurements. We applied this procedure to state-of-the-art neural network architectures on miscellaneous hardware. One of the main applications and novelties is the measurement of algorithmic power efficiency. The objective is to allow researchers to grasp their algorithms' efficiencies better. This methodology was developed to explore trade-offs between energy usage and accuracy in neural networks. It is also useful when fitting hardware for a specific task or to compare two architectures more accurately, with architecture exploration in mind.

This article proposes a new integrated analog implementation of the Pan–Tompkins algorithm. This algorithm, generally implemented in the digital domain at the cost of higher power consumption, is one of the most efficient for QRS detection in electrocardiographic signals. This circuit has been designed for use on small mammals like rats for the study of pulmonary arterial hypertension. The specificities of the architecture proposed in this article are a sub-threshold-operated architecture to perform the amplification, noise filtering, and differentiation of the signal in a unique block to limit the power consumption; an analog squarer; and an analog monostable reshaping-circuit followed by a digital counter clocked by an ultra-low power relaxation oscillator. Compared with the state of the art, this circuit, designed with the X-FAB xh018 180 nm CMOS technology, presents one of the lowest power consumptions currently reported, at 28.5 nW, 76% of which is consumed in the current, voltage, and time references. Post-layout simulation results show a reliable 98.57% heart beat detection accuracy using the MIT-BIH arrhythmia database and 99.85% accuracy for healthy sinus rhythm electrocardiograms. The robustness of the circuit is also investigated, and mitigating solutions are proposed for each critical block.