Digital predistorsion (DPD) is a commonly used approach to compensate for the power amplifiers (PA) nonlinearities and memory effects as well as to improve its power efficiency. To alleviate the restriction brought by high peak-to-average power ratio (PAPR) of input signals, crest factor reduction (CFR) is needed for higher efficiency. In modern communication systems, power of transmitted signals gets lower, which makes complexities of CFR and DPD become nonnegligible. This article proposes a new approach to realize a joint CFR and DPD model using neural networks (NN). The modeling accuracy is guaranteed by a new proposed augmented iterative learning control (AILC) algorithm for the NN training signals. Compared with conventional ILC, the proposed AILC is shown more robust according to simulation and experimental results. The proposed AILC-based NN-CFRDPD is experimentally evaluated on different test benches.

This letter proposes a method to study the tradeoff between the power amplifier (PA) power efficiency and the corresponding digital predistortion (DPD) model complexity needed for its linearization. The linearization performance estimated with the adjacent channel power ratio (ACPR) is treated as a control variable. In order to study at different PA operating points (OPs), an algorithm is proposed to trace approximate Pareto fronts of the ACPR versus the DPD model number of coefficients. Crest factor reduction is applied when the backoff of the OP is less than the peak-to-average power ratio (PAPR) of the long-term evolution (LTE) signal. Experimental results on a PA with an LTE signal give interesting insights on the relationship between DPD complexity and PA power efficiency.

The power efficiency and the linearity of a power amplifier (PA) depend on its operating point. A high efficiency generally corresponds to poor linearity. To optimize the efficiency/linearity tradeoff, crest factor reduction (CFR) techniques are classically implemented along with digital predistortion (DPD) to control the PA operating point. Joint CFR/DPD can be realized with a single model so that the running complexity of the CFR is negligible. This article fully explores the clipping-and-bank-filtering (CABF) method for joint CFR/DPD and extends it to the multicarrier case with validation of experimental results. Compared with conventional approaches, it provides either better linearization performance or lower complexity at the same PA operating point. The study is completed with a discussion on the choice of windows in the filter bank. The proposed CABF-based joint CFR/DPD model is then experimentally evaluated on a test bench with two PAs using single-carrier and two-carrier 20-MHz long-term evolution signals as the stimulus.

This paper presents a 14-bit Incremental Sigma-Delta \((\varSigma \varDelta) \) analog-to-digital converter suitable for column wise integration in a CMOS image sensor. A two step conversion is performed to improve the conversion speed. As the same \(\varSigma \varDelta \) modulator is used for both steps, the overall complexity is reduced. Furthermore, the use of inverter-based amplifiers instead of operational transconductance amplifier facilitates the integration within the column pitch and decreases power consumption. MonteCarlo simulations have been done in order to validate the design of the inverter. The proposed ADC is designed in \(0.18\,\upmu \hbox {m}\) CMOS technology. The simulation is performed with a 1.8 V voltage supply, a 20 MHz system clock frequency and an oversampling ratio (OSR) of 70, and achieves a power consumption is \(460 \, \upmu \hbox {W}\), a SNDR of 85.4 dB at a sampling rate of 250 kS/s.