Security and privacy of data are one of the prime concerns in today’s Internet of Things (IoT). Conventional security techniques like signature-based detection of malware and regular updates of a signature database are not feasible solutions as they cannot secure such systems effectively, having limited resources. Programming languages permitting immediate memory accesses through pointers often result in applications having memory-related errors, which may lead to unpredictable failures and security vulnerabilities. Furthermore, energy efficient IoT devices running on batteries cannot afford the implementation of cryptography algorithms as such techniques have significant impact on the system power consumption. Therefore, in order to operate IoT in a secure manner, the system must be able to detect and prevent any kind of intrusions before the network (i.e., sensor nodes and base station) is destabilised by the attackers. In this article, we have presented an intrusion detection and prevention mechanism by implementing an intelligent security architecture using random neural networks (RNNs). The application’s source code is also instrumented at compile time in order to detect out-of-bound memory accesses. It is based on creating tags, to be coupled with each memory allocation and then placing additional tag checking instructions for each access made to the memory. To validate the feasibility of the proposed security solution, it is implemented for an existing IoT system and its functionality is practically demonstrated by successfully detecting the presence of any suspicious sensor node within the system operating range and anomalous activity in the base station with an accuracy of 97.23%. Overall, the proposed security solution has presented a minimal performance overhead.

We propose objective and robust measures for the purpose of classification of “vaginal vs. cesarean section” delivery by investigating temporal dynamics and complex interactions between fetal heart rate (FHR) and maternal uterine contraction (UC) recordings from cardiotocographic (CTG) traces. Multivariate extension of empirical mode decomposition (EMD) yields intrinsic scales embedded in UC-FHR recordings while also retaining inter-channel (UC-FHR) coupling at multiple scales. The mode alignment property of EMD results in the matched signal decomposition, in terms of frequency content, which paves the way for the selection of robust and objective time-frequency features for the problem at hand. Specifically, instantaneous amplitude and instantaneous frequency of multivariate intrinsic mode functions are utilized to construct a class of features which capture nonlinear and nonstationary interactions from UC-FHR recordings. The proposed features are fed to a variety of modern machine learning classifiers (decision tree, support vector machine, AdaBoost) to delineate vaginal and cesarean dynamics. We evaluate the performance of different classifiers on a real world dataset by investigating the following classifying measures: sensitivity, specificity, area under the ROC curve (AUC) and mean squared error (MSE). It is observed that under the application of all proposed 40 features AdaBoost classifier provides the best accuracy of 91.8% sensitivity, 95.5% specificity, 98% AUC, and 5% MSE. To conclude, the utilization of all proposed time-frequency features as input to machine learning classifiers can benefit clinical obstetric practitioners through a robust and automatic approach for the classification of fetus dynamics.

Security and privacy of data are one of the prime concerns in today's embedded devices. Primitive security techniques like signature-based detection of malware and regular update of signature database are not feasible solutions as they cannot secure such systems, having limited resources, effectively. Furthermore, energy efficient wireless sensor modes running on batteries cannot afford the implementation of cryptography algorithms as such techniques have significant impact on the system power consumption. Therefore, in order to operate wireless embedded devices in a secure manner, the system must be able to detect and prevent any kind of intrusions before the network (i.e. sensor nodes and base station) is destabilized by the attackers. In this paper, we have presented an intrusion detection mechanism by implementing an intelligent security architecture using Random Neural Networks (RNN). To validate the feasibility of the proposed security solution, it is implemented for an existing wireless sensor network system and its functionality is practically demonstrated by successfully detecting the presence of any suspicious sensor node and anomalous activity in the base station with high accuracy and minimal performance overhead

Automatic vehicle type recognition (make and model) is very useful in secure access and traffic monitoring applications. It compliments the number plate recognition systems by providing a higher level of security against fraudulent use of number plates in traffic crimes. In this paper we present a simple but powerful probabilistic framework for vehicle type recognition that requires just a single representative car image in the database to recognize any incoming test image exhibiting strong appearance variations, as expected in outdoor image capture e.g. illumination, scale etc. We propose to use a new feature description, local energy based shape histogram 'LESH', in this problem that encodes the underlying shape and is invariant to illumination and other appearance variations such as scale, perspective distortions and color. Our method achieves high accuracy (above 94%) as compared to the state of the art previous approaches on a standard benchmark car dataset. It provides a posterior over possible vehicle type matches which is especially attractive and very useful in practical traffic monitoring and/or surveillance video search (for a specific vehicle type) applications.

Embedded processors are key building blocks for IoT platforms. Multiply-Accumulate (MAC) units are vital arithmetic circuits in several applications performed by the processors including digital signal processing (DSP). It is necessary to reduce the power consumed by the processor. In this paper, the design and implementation of 32-bit MAC unit optimized for low-power budget targeting IoT processors is introduced. The proposed MAC unit is capable of performing several 16bit, dual 16-bit, and 32-bit MAC operations that can be carried out on signed and unsigned numbers with up to three operands involved. The performance of MAC unit is analyzed in terms of delay and power. The unit is described in VHDL, implemented and simulated on Vivado and tested using Nexys 4 DDR board featuring Xilinx's Artix-7 FPGA.