Stochastic Computing has attracted extensive attention in the deployment of neural networks at the edge due to its low hardware cost and high fault tolerance. However, traditional stochastic computing requires a long random bit stream to achieve sufficient numerical precision. The long bit stream, in turn, increases the network inference time, hardware cost, and power consumption, which limits its application in executing tasks such as handwritten recognition, speech recognition, image processing, and image classification at the near-sensor end. To realize high-energy-efficiency and low-cost hardware neural networks at the near-sensor end, a hardware optimization design of convolutional neural networks based on the hybrid encoding of deterministic encoding and binary encoding is proposed. By transforming the output signals from the sensor into deterministic encoding and co-optimizing the network training process, a low-cost and high-energy-efficiency convolution operation network is achieved with a shorter bit stream input. This network can achieve good recognition performance with an extremely short bit stream, significantly reducing the system’s latency and energy consumption. Compared with traditional stochastic computing networks, this network shortens the bit stream length by 64 times without affecting the recognition rate, achieving a recognition rate of 99% with a 2-bit input. Compared with the traditional 2-bit stochastic computing scheme, the area is reduced by 44.98%, the power consumption is reduced by 60.47%, and the energy efficiency is increased by 12 times. Compared with the traditional 256-bit stochastic computing scheme, the area is reduced by 82.87%, and the energy efficiency is increased by 1947 times. These comparative results demonstrate that this work has significant advantages in executing tasks such as image classification at the near-sensor end and edge devices.

Stochastic circuits offer the benefits of small area and lower power consumption. However, as the bit width of the operands increases, the area and latency of stochastic circuits also need to increase exponentially to meet the precision requirements, resulting in a decrease in performance. This brief introduces a low-cost and high-speed parallel approximate stochastic computing multiplier (PASCM), which takes binary streams as both inputs and outputs. The PASCM is suitable for multiplication operations with multi-bit width. In order to further enhance the accuracy of the PASCM, an error compensation mechanism has been proposed. To verify the performance of PASCM, validation was conducted on FPGA. The experimental results indicate that the proposed design exhibits significant area and latency advantages among existing multipliers. Take 8-bit as an example, the PASCM shows a 48.33%, 18.61%, 45.74%, and 57.95% reduction in Look-Up Table (LUT), latency, power delay product (PDP), and area delay product (ADP), respectively, compared to the 8-bit precise binary multiplier implemented using an IP core. To further validate the design, the PASCM was constructed into Multiply-Accumulate units (MAC) and applied to several image processing algorithms on FPGA. The proposed multiplier showed excellent results in terms of peak signal-to-noise ratio (PSNR) and mean structural similarity index (MSSIM), with some algorithms achieving complete consistency with binary computation results, and the hardware performance also surpasses the most advanced designs.