This study investigates the performance of lattice-structured heat sinks based on BCCz unit cells in comparison to conventional straight-fin and pin-fin designs. Various lattice configurations were explored. Numerical simulations and experimental evaluations were carried out to analyze thermal resistance, pressure drop, and temperature distribution under different operating conditions. Among the designs, the BCCz configuration with a circular cross-section was identified as the most promising candidate for integration into the final heat sink demonstrator, offering reliable and consistent performance. A prototype using the BCCz lattice structure was additively manufactured, alongside a conventional design for comparison. The results highlight the superior heat dissipation capabilities of lattice structures, achieving up to a 100% improvement in thermal performance at high flow rates and up to 300% at low flow rates compared to a conventional straight-fin heat sink. However, the pressure drop generated by the lattice structures remains a challenge that must be addressed. This work underscores the potential of optimized lattice-based heat exchangers to meet the severe thermal management requirements of railway power electronics.

This article presents a method for detecting the temperature distribution of two parallelized Silicon Carbide (SiC) MOSFETs. Two thermally sensitive electrical parameters (TSEPs), namely the on-state resistance ($R_{dson}$) and the threshold voltage ($V_{th}$), are introduced. A comparison of the temperatures interpolated by $V_{th}$ and $R_{dson}$ shows disparity, enabling the detection of individual junction temperatures. $V_{th}$ instability and its measurement are discussed for SiC devices. Experimental results show that, depending on the instability of the $V_{th}$ and the sensitivity of the two TSEPs at certain temperatures, a combination of different TSEPs could be a solution for extracting the maximum junction temperature of parallelized devices.

This article presents a method for detecting temperatures distribution of two Silicon Carbide (SiC) MOSFETs parallelized. Two Thermally Sensitive Electrical Parameters (TSEP), namely the on-state resistance (Rdson) and the threshold voltage (Vth), are introduced. Comparison of temperatures interpolated by Vth and Rdson shows disparity which can lead to individual junction temperature detection. Vth instability and its measurement are discussed for SiC devices. Experimental results show that depending on the instability of the Vth and the sensitivity of the two TSEPs at certain temperatures, the combination of different TSEPs could be a solution to extract maximum junction temperature of parallelized devices.