Fe therapy can be effective in heart failure patients both with and without anaemia. However, the role of Fe therapy in such patients is still uncertain. In this review, the aim was to evaluate the efficacy and safety of Fe therapy in adult patients with heart failure who have reduced ejection fraction (HFrEF). Multiple databases (PubMed, Medline, EMBASE, the Cochrane Library and Clinical Trials) were searched up to December 2017 and the reference lists of relevant articles obtained from the search were reviewed. Data extracted from randomised control trials (RCT) selected for the review were pooled using a fixed effects model or a random effects model, according to heterogeneity between trials. Nine RCT were included in this meta-analysis which included a total of 789 patients who received Fe therapy and who in turn were compared with 585 controls. There was significant improvement in the 6-min walk test (19·05 m, 95 % CI 10·48, 27·62) and peak VO₂/kg (0·93 ml/kg per min, 95 % CI 0·16, 1·69) in the Fe supplementation arm. With Fe therapy, fewer patients were hospitalised for heart failure (OR: 0·42, 95 % CI 0·27, 0·65), but no relationship was found for total re-hospitalisation (OR: 0·70, 95 % CI 0·32, 1·51) or mortality (OR: 0·70, 95 % CI 0·38, 1·28). Fe therapy has the potential to improve exercise tolerance, reduce re-hospitalisations for patients with HFrEF having Fe deficiency. In addition, Fe supplementation was found to be safe, with no increased rate of adverse events.

The fast switching of gallium nitride high mobility transistor (GaN HEMT) results in high dv/dt and severe EMI issues, requiring a trade-off with the switching power loss. Three-stage gate drive (TSGD) can mitigate the conflict between switching speed and losses, but it is challenging to achieve minimal switching loss under the existing TSGD strategy due to the nonlinear parasitic capacitance of GaN HEMT. To address this issue, this paper proposes a minimal switching loss TSGD strategy based on a dynamic dv/dt switching model, which can achieve minimal switching loss. Firstly, based on the charge conservation principle, piecewise linear equivalent values for the parasitic capacitances of GaN HEMT are calculated. Based on the result, analytical expressions for the transient voltage and current in each switching stage are derived, which forms the dynamic dv/dt switching model and provides detailed analysis for the dv/dt nonlinearity. Furthermore, analytical expressions for switching loss during each stage are calculated, establishing the quantitative relationship between switching loss and drive conditions. By minimizing the total loss, the required driving currents and switching timings are determined. Finally, the MSL-TSGD strategy is proposed. Experimental results demonstrate that the proposed method reduces the turn-on loss by 18.6%, and reduces the turn-on delay by 29.3%.

Achieving low switching loss is critical for high-frequency gallium nitride (GaN)-based power converters due to the compact packaging and limited heat dissipation capacity of GaN devices. Focusing on minimizing the switching loss, this article proposes an adaptive three-stage gate driver (ATSGD) for GaN high electron mobility transistor (GaN HEMT). By providing a three-stage driving current within the Miller plateau (MP) stage, the proposed ATSGD can achieve a near-constant dV/dt, thus minimizing the switching loss under specific peak dV/dt constraints. Utilizing peak MP voltage tracking (PMPVT) and quick voltage tailing suppression (QVTS) techniques, the driver dynamically determines optimal switching timings for the three-stage driving currents in real time. Therefore, the extra losses caused by slow dV/dt start-up and voltage tailing effect are minimized under dynamic operation conditions. Fabricated in a $0.18~{\mu }$ m bipolar-CMOS-double-diffused metal oxide semiconductor (BCD) process, the proposed driver reduces the total switching loss by 36.4% under 400 V/15 A with a peak dV/dt of 45 V/ns, benefiting from a 46.1% reduction in slow dV/dt start-up loss and an 88.7% reduction in voltage tailing loss compared with conventional gate drivers.

Forsilicon carbide (SiC) MOSFET applications, it has been a constant challenge to address the trade-off among drain-source voltage slew rate (dv ${}_{\mathbf {ds}}$ /dt), drain-source voltage spike, and turn-off loss. The existing active gate drivers (AGDs) have not considered the influence of dynamically varying drain current, resulting in increased turn-off loss and voltage spike. To address this issue, this paper proposes a cross-cycle dynamic active gate driver (CDAGD) that features constant (dv ${}_{\mathbf {ds}}$ /dt) ${}_{\mathbf {max}}$ and spike under dynamic drain current. By deriving the quantitative relationship among the gate current,drain current, (dv ${}_{\mathbf {ds}}$ /dt) ${}_{\mathbf {max}}$ , and voltage spike, the optimal gate currents in different switching stages are determined. Furthermore, the CDAGD incorporates a cross-cycle gate current regulator (CCGCR) to generate the required gate currents in different stages, and a dynamic switching timing controller (DSTC) to locate the optimal timing of the stages. With the CDAGD providing the optimal gate current, the turn-off loss is minimized with reduced dv ${}_{\mathbf {ds}}$ /dt and spike.Fabricated in a $0.18\mu $ m BCD process, the CDAGD chip achieves a maximum reduction in turn-off loss of 72.2% and 37.9% compared with the conventional gate driver (CGD) and AGD under varying drain current. A 45.9% reduction in turn-off time is also achieved with the proposed gate driver.

Conventional successive approximation recursive (SAR) control hybrid low-dropout regulators (LDOs) have problems such as significant reverse overshoot and discontinuous current switching. Based on trajectory optimization in the phase plane, this paper presented initial/last-state-correlated SAR control to address the aforementioned issues. Firstly, the operating principles of the conventional SAR controller are elucidated, which is depicted by a finite state machine (FSM). Secondly, large reverse overshoot and discontinuous current switching of the SAR control hybrid LDO are analyzed through the phase plane trajectory. Then, the initial/last-state SAR control is proposed by FSM to optimize the trajectory, thereby reducing the reverse overshoot and smoothing current switching. Finally, a series of design challenges of the initial/last-state-correlated SAR control are discussed. Implemented at 1.11 mm × 0.567 mm in a 180 nm bipolar-CMOS-DMOS (BCD) process, under a 0.1 nF output capacitor, the 6-bit hybrid LDO in this paper achieved an output voltage overshoot of 76 mV and a transient time of 18.8 μs at a 152 mA load current change. The experimental result demonstrates the distinct dynamic response advantages of the initial/last-state SAR control.