Digital Peak Current Mode (DPCM) control is widely used for DC-DC converters operating in Continuous Current Mode (CCM). However, Current Tracking Delay (CTD) in the system is normally neglected in the modelling stage, which leads to poor compensator design and degraded performance. This paper investigates CTD effect in boost converter with different DPCM controls. Based on dynamic relationship between the reference current and actual inductor current, the CTD transfer functions are derived, which improves the accuracy of Small Signal Model (SSM). Since CTD degrades the phase margin of the system, equivalent migration of Right Half Plane (RHP) zero is proposed to model CTD effect. This method is very simple and straightforward, which facilitates the compensator design. Furthermore, two novel DPCM control strategies with minimized CTD are proposed, and they are based on duty cycle restriction and duty cycle extension, respectively. Both controls greatly reduce the CTD effect and improve the response speed. Besides, the duty cycle extension benefits from an Extended Pulse Width Modulation (ExPWM). This optimizes the calculation algorithm and speed, while improves the time margin for digital calculations. Combined with the proposed models and controls, the CTD effect is greatly reduced. The effectiveness is verified through detailed simulations and experiments.

This article reveals parasitics-induced current distortion (PCD) effect in discontinuous conduction mode boost power factor (PF) correction (PFC) converter. With consideration of parasitics, accurate inductor current is derived through total differential functions of line voltage, output voltage and duty cycle. Furthermore, the proposed current model is used to analyze PFC converter under conventional sensorless average current mode (SACM) control, which is achieved by a variable duty cycle. It is found that parasitics have considerable influence to the input current, and PCD leads to a degraded PF. In order to solve this issue, a current reshaping strategy is proposed to reduce the PCD phenomenon. Based on the damped current equations, a compensation gain is derived to reshape the input current, which reduces the current damping and distortion caused by parasitics. Both the PCD phenomenon and the current reshaping strategy are verified by simulations and experiments.

This article proposes a unified pulsewidth-cycle (UPWC) control strategy to achieve mixed-mode operation and consistent valley switching (VS) for boost power factor correction converter. Compared with conventional single-mode controllers, it has a unified scheme to achieve single discontinuous conduction mode (DCM), single critical conduction mode (CRM), or mixed DCM/CRM operations in each half-line cycle. To regulate the input current as a sinusoid, the UPWC controller adopts a variable pulsewidth and a near-constant switching cycle under DCM, while adopts a constant pulsewidth and a variable switching cycle under CRM. To facilitate analysis, normalized mapping of operation modes is provided, along with the final pulsewidth and switching cycle. Furthermore, to ensure consistent VS, a controlled zero current detection method is proposed to fix the turn-on point of the power switch. No matter in DCM or CRM, consistent VS reduces both the switching loss and current distortion caused by parasitic resonance. To further reduce the current distortion caused by fixing the turn-on point, a compensation gain is provided that reshapes the input current as a sinusoid. Finally, through mixed DCM/CRM operation and consistent VS, the proposed UPWC controller achieves preferable performances in the power range, efficiency, power factor, and current distortion.

This article presents an optimal duty ratio assisted pulse frequency modulation control for very high frequency isolated class E dc–dc converter to achieve both continuous power flow and optimal switch timing. The continuous power flow significantly reduces output ripple of the converter, while the optimal switch timing guarantees consistent zero-voltage-switching (ZVS) and minimized reverse conduction loss. To pave the way for the proposed control, a resonant fitting model is established for deriving the optimal duty ratio and output power under dynamic switching frequency. The optimal duty ratio is calculated according to zero-crossing points of the switching node voltage ( v_ds ), and it aims to turn on the power switch once v_ds reaches zero. This ensures consistent ZVS while preventing reverse conduction of gallium nitride (GaN) high electron mobility transistor (HEMT) when the switching frequency changes. Furthermore, the proposed control is integrated with on/off modulation to extend load range of the converter. A 10–18 MHz prototype is built to verify effectiveness of the proposed control. Compared with conventional PFM control, the proposed control reduces the power loss by 35.9% at 40% load while maintains continuous power flow.

The fast switching of gallium nitride high mobility transistor (GaN HEMT) results in high dv/dt and severe EMI issues, requiring a trade-off with the switching power loss. Three-stage gate drive (TSGD) can mitigate the conflict between switching speed and losses, but it is challenging to achieve minimal switching loss under the existing TSGD strategy due to the nonlinear parasitic capacitance of GaN HEMT. To address this issue, this paper proposes a minimal switching loss TSGD strategy based on a dynamic dv/dt switching model, which can achieve minimal switching loss. Firstly, based on the charge conservation principle, piecewise linear equivalent values for the parasitic capacitances of GaN HEMT are calculated. Based on the result, analytical expressions for the transient voltage and current in each switching stage are derived, which forms the dynamic dv/dt switching model and provides detailed analysis for the dv/dt nonlinearity. Furthermore, analytical expressions for switching loss during each stage are calculated, establishing the quantitative relationship between switching loss and drive conditions. By minimizing the total loss, the required driving currents and switching timings are determined. Finally, the MSL-TSGD strategy is proposed. Experimental results demonstrate that the proposed method reduces the turn-on loss by 18.6%, and reduces the turn-on delay by 29.3%.

For very high frequency (VHF) class 2 inverter, conventional design method requires complex tuning for parameters. Without fully quantitative calculations, the tuning highly depends on experience that cannot achieve optimal design. In this paper, a target function design strategy is proposed based on quantitative harmonic weighting, which simplifies the design procedures and minimizes the switch voltage stress. Firstly, the target switch voltage with minimized peak value is derived by optimizing the harmonic weighting. With the result, the power switch is modeled as a voltage source to simplify the calculations, where the branch currents are solved to provided fully quantitative analysis. Based on the analysis, optimal features of switching node impedance are derived to achieve the target switch voltage. Additionally, basic constrains of the resonant tank are analyzed to reduce circling currents. Combining the optimal features and basic constrains of the resonant tank, the circuit parameters are calculated directly, which minimizes the switch voltage stress and improves power efficiency. Compared with conventional design, a 27.12MHz prototype demonstrates 10.2% reduction in average switch voltage stress and 7.2% improvement in average efficiency.