This article presents an optimal duty ratio assisted pulse frequency modulation control for very high frequency isolated class E dc–dc converter to achieve both continuous power flow and optimal switch timing. The continuous power flow significantly reduces output ripple of the converter, while the optimal switch timing guarantees consistent zero-voltage-switching (ZVS) and minimized reverse conduction loss. To pave the way for the proposed control, a resonant fitting model is established for deriving the optimal duty ratio and output power under dynamic switching frequency. The optimal duty ratio is calculated according to zero-crossing points of the switching node voltage ( v_ds ), and it aims to turn on the power switch once v_ds reaches zero. This ensures consistent ZVS while preventing reverse conduction of gallium nitride (GaN) high electron mobility transistor (HEMT) when the switching frequency changes. Furthermore, the proposed control is integrated with on/off modulation to extend load range of the converter. A 10–18 MHz prototype is built to verify effectiveness of the proposed control. Compared with conventional PFM control, the proposed control reduces the power loss by 35.9% at 40% load while maintains continuous power flow.

The fast switching of gallium nitride high mobility transistor (GaN HEMT) results in high dv/dt and severe EMI issues, requiring a trade-off with the switching power loss. Three-stage gate drive (TSGD) can mitigate the conflict between switching speed and losses, but it is challenging to achieve minimal switching loss under the existing TSGD strategy due to the nonlinear parasitic capacitance of GaN HEMT. To address this issue, this paper proposes a minimal switching loss TSGD strategy based on a dynamic dv/dt switching model, which can achieve minimal switching loss. Firstly, based on the charge conservation principle, piecewise linear equivalent values for the parasitic capacitances of GaN HEMT are calculated. Based on the result, analytical expressions for the transient voltage and current in each switching stage are derived, which forms the dynamic dv/dt switching model and provides detailed analysis for the dv/dt nonlinearity. Furthermore, analytical expressions for switching loss during each stage are calculated, establishing the quantitative relationship between switching loss and drive conditions. By minimizing the total loss, the required driving currents and switching timings are determined. Finally, the MSL-TSGD strategy is proposed. Experimental results demonstrate that the proposed method reduces the turn-on loss by 18.6%, and reduces the turn-on delay by 29.3%.

For very high frequency (VHF) class 2 inverter, conventional design method requires complex tuning for parameters. Without fully quantitative calculations, the tuning highly depends on experience that cannot achieve optimal design. In this paper, a target function design strategy is proposed based on quantitative harmonic weighting, which simplifies the design procedures and minimizes the switch voltage stress. Firstly, the target switch voltage with minimized peak value is derived by optimizing the harmonic weighting. With the result, the power switch is modeled as a voltage source to simplify the calculations, where the branch currents are solved to provided fully quantitative analysis. Based on the analysis, optimal features of switching node impedance are derived to achieve the target switch voltage. Additionally, basic constrains of the resonant tank are analyzed to reduce circling currents. Combining the optimal features and basic constrains of the resonant tank, the circuit parameters are calculated directly, which minimizes the switch voltage stress and improves power efficiency. Compared with conventional design, a 27.12MHz prototype demonstrates 10.2% reduction in average switch voltage stress and 7.2% improvement in average efficiency.

For multiphase voltage regulators (MPVRs) with conventional phase shedding and transient voltage clamping (TVC), transient response is limited by intrinsic clamping error, reduced converter loop feedback and phase shedding delay. To address the issues, this article proposes differentiation-triggered TVC (DTVC) and quasi-zero-delay phase shedding (QZDPS) schemes for joint transient enhancement of the MPVR. To eliminate the intrinsic clamping error, the DTVC scheme adopts a d v /d t circuit to detect output voltage differentiation in advance. Besides, converter load response is accelerated by saturated drive modulation in synchrony with the DTVC current injection. To take full advantage of multiphase current slew rate, the QZDPS is achieved with instant load estimation. Furthermore, to make DTVC compatible with QZDPS, the state transition logics for multiphase drive modulation are established with DTVC transient flags and QZDPS signal. It allows for a joint transient enhancement that pushes the load transient response of the MPVR to the physical boundary. According to experimental results, the proposed scheme improves the transient voltage deviation and response time by 38% and 75%, respectively. Along with the enhanced transient, the transient energy loss is reduced by 66%.

Power losses of switches and inductors are consistent challenges that hinder the development of high-frequency power supply in package (PSiP). This paper investigates the roadmap for power loss optimizations of switches and inductors in high-frequency PSiPs. Firstly, a size and parallel quantity design method to reduce power loss in an integrated Si LDMOSFET is provided with comprehensive consideration of switching frequency and power levels. Secondly, quality factors of different air-core inductors are analyzed with consideration of geometric parameters and skin effect, which provides the winding structure optimization to reduce power losses. The power losses of the integrated Si LDMOSFET and air-core inductors are both reduced to less than 10% of the output power at 1~100 MHz switching frequency and 0.1~10 W power level. Finally, based on the above optimizations, power losses of switches and inductors are calculated with switching frequency and power level. Combining the calculated results, this paper predicts the efficiency boundaries of PSiPs. Upon efficiency normalization with consideration of input and output voltage levels, all the predictions are consistent with the published literature. The efficiency predication error is 1~15% at 1~100 MHz switching frequency and 0.1~10 W power level. The above power loss optimizations improve the efficiency, which provides potential roadmaps for achieving high-frequency PSiPs.

In discontinuous conduction mode boost converters, the switching-node voltage oscillates after the inductor current reaches zero, leading to fluctuating power loss. To investigate this, a circulating energy model is first proposed. Accurate power loss is analyzed with consideration of oscillation damping effect, reverse conduction of power switch, and nonlinear capacitance effect. Analysis shows that the loss can be minimized when the switch is turned on at specific switching-node voltage valleys. Therefore, to minimize the power loss, a grouped valley switching (GVS) control is proposed to count the valleys and turn on the switch at the optimal valley. However, dynamic changes in valleys will cause frequency hopping, resulting in degraded total harmonic distortion (THD) in input current. To address this issue, the GVS controller turns on the switch at constant valleys in a half-line cycle, while adaptively calculating the on -time with online tracked oscillation duration. For efficiency improvement, the optimal valleys are grouped and tuned based on a comprehensive power loss analysis. Experimental results validate the effectiveness of the proposed control. Compared with conventional variable on -time controls, the proposed control improves an average efficiency of 0.4% across the entire power range under 110/220 VAC input. The THD is below 3.1% at 250 W rated power.