This paper presents a low temperature coefficient (TC) CMOS BGR for high-performance multi-channel analog-to-digital converter (ADC) working under wide temperature range. Besides the logarithmic compensation, both leakage and piecewise curvature compensation are implemented to extend its operating temperature range and keep its low TC. A β -compensation technique is used to cancel the PTAT and non-PTAT spread of the output due to variation of limited β in the Bipolar Junction Transistors. Moreover, the error-correcting resistors are implemented to eliminate the first-order inaccuracy of the output. The BGR designed in 0.18 μm 1.8-/5-V CMOS process has a minimum simulated TC of 0.42ppm/°C over a wide temperature of -60 °C to 150 °C, making it appropriate to provide reference voltage for a high-precision ADC for sensor interface.

This article introduces a high-voltage (HV) compliant, energy-efficient current-mode stimulator featuring a proposed boost-based dynamic voltage supply (DVS) to minimize the voltage dropout. The stimulator employs an activate-on-demand asynchronous strategy, instructing the boost converter to generate the dynamically increased high voltage that tracks the electrode’s voltage drop, thus achieving a near-adiabatic stimulation. The strategy relies on measuring the boost’s varying voltage conversion ratio (VCR), which is facilitated by an 8-bit voltage ratio quantizer (VRQ) proposed in this article. Furthermore, the boost converter employs a low-power, fast-speed, HV gate driver (HVGD) to control its p-type power switch that connects the inductor to the HV output. This article also presents a dedicated digital circuit that generates the pulse signals for controlling the n-type power switch and the HVGD. This digital circuit is driven by a five-phase clock from a current-starved ring oscillator. A highly efficient rotationally symmetric level shifter is utilized for the ring oscillator’s output, translating its level and improving its rise/fall time. The boost converter reaches a peak efficiency of 90.2%, enabling the stimulator to achieve an end-to-end energy efficiency of up to 86% during a biphasic stimulation of 6 mA. The stimulator IC, fabricated using 0.18-m bipolar–CMOS–DMOS (BCD) technology, occupies a compact area of 2.16 mm ² . It exhibits low static power consumption at 1.78 W, promising battery-powered implants with an extended lifetime and a reduced form factor.

A dynamic comparator reset scheme based on the flying capacitor is proposed. The reset power used to charge the integration nodes of the comparator is nearly halved by exploiting the existent integration capacitors with only a single D-flip-flop and few switches. The proposed reset scheme improves the energy efficiency while the small CLK-OUT delay of the dynamic comparator is maintained. The prototype comparators with the conventional or the proposed reset scheme are fabricated in a 22-nm bulk CMOS process. The measurement results of the delay, input-referred noise, and energy consumption show that the flying-capacitor-based reset scheme boosts the overall performance of both the conventional StrongARM and Elzakker’s comparator by about 1.8-times.

A low-power digital readout integrated circuit (DROIC) for silicon diode uncooled infrared focal plane arrays (IRFPAs) is presented. The DROIC adopts a 14-bit column-level extended-counting analog-to-digital converter (ADC) based on a cascade of a coarse continuous-time Σ-ADC and a fine single-slope ADC. While the weak detector signal is integrated, the coarse conversion is implemented by a feedback current-steering digital-to-analog converter (IDAC), which shortens the signal chain and reduces the bandwidth requirement for the op-amp, to reduce power consumption. Besides, the ramp signal of the fine conversion is generated locally by an additional column-level IDAC, which matches the coarse conversion IDAC to decrease the DNL. Also, a low-power non-uniformity calibration circuit is adopted to compensate the non-uniformity of the IRFPA and adjust the ADCfs input signal range. The DROIC with 1024 ×768 pixel array is fabricated in a 0.18μm CMOS process. The experimental results demonstrate the DROIC consumes 109mW. The noise is 1.7LSB and the equivalent input noise voltage of the column circuit is about 2.1μVrms. The INL and DNL are less than +6.1LSB/.4.4LSB and +0.40LSB/.0.38LSB, respectively.