The Internet of Things (IoT) is an interface with the physical world that usually operates in random-sparse-event (RSE) scenarios. This article discusses main challenges of IoT chips: power consumption, power supply, artificial intelligence (AI), small-signal acquisition, and evaluation criteria. To overcome these challenges, many works recently aimed at IoT system design have emerged. This work reviews the architecture and circuit innovations that have contributed to IoT developments. This paper does not cover security of IoT. Event-driven architectures and nonuniform sampling ADCs significantly reduce the long-term average power. Besides, embedding AI engines in IoT nodes (AIoT) is one critical trend. The computing-in-memory technique improves the energy efficiency of the AI engine. Asynchronous spike neural networks (ASNNs) AI engines show low power potential. In addition to data processing, small-signal acquisition is also critical. The charge-domain analog-front-end (AFE) techniques such as floating inverter-based amplifiers improve energy efficiency. In addition to the above low power and high energy efficiency technologies, energy harvesting can also enhance the lifetime of AIoT devices. This article discusses recent ambient RF and natural energy harvesting approaches and high-efficiency DC-DC with a wide load range. Finally, novel evaluation criteria are introduced to establish benchmark standards for AIoT chips.

This article presents a 148-nW always-on wake-up system that drastically reduces the system power consumption of Internet of Things (IoT) sensor nodes while oftentimes operating in random-sparse-event (RSE) scenarios. To significantly reduce the long-term average (LTA) power consumption and realize multiapplication and intelligent event detection, three techniques are proposed: 1) In a three-stage pipelined event-driven architecture, a frame generator and a convolutional neural network intelligent inference engine (CNN IIE) in stage III are event-driven by the preliminary detectors in stage II, and the detectors are triggered by a level-crossing (LC) analog-to-digital converter (ADC), i.e., stage I, dramatically reducing the overall power consumption. 2) The clock-free pulse-based instant rate of change (IROC) feature extractor directly processes the asynchronous pulses of the LC-ADC outputs in the temporal domain instead of utilizing a conventional power-hungry frequency-domain method. 3) A reconfigurable IROC, the frame generator, and the CNN IIE provide adaptive intelligence for various IoT events, enhancing the accuracy of multipurpose detection with ultralow power. We demonstrate two artificial intelligence IoT (AIoT) applications at 0.6-V V _DD . For electrocardiogram (ECG) recognition, one example works at a typical event rate (ER) of ~4800/h, with an active power of 1.68 $\mu \text{W}$ and a precision of up to 99%; the other is used for keyword spotting (KWS), where the chip achieves 378 nW at ~720/h ER and 94% accuracy. The LTA power is bounded to 148 nW, while the event-driven chip is on call and waiting for events; this chip dominates the AIoT device battery life in RSE scenarios.

This work presents an ultra-low-power software-defined always-on wake-up system to drastically decrease the system power of Internet of Things (IoTs) devices, which usually operate in random-sparse-event (RSE) scenarios. It mainly thanks to a clock-free time-shielding level-crossing ADC (TS-LCADC), software-defined clock-free multi-function detectors, and an asynchronous pipelined event-driven architecture. First, by quantifying RSE noisy signals with clock-free adaptive sampling in a signal-noise-rejecting manner, the proposed TS-LCADC reduces number of sampling points and power, and consumes only 41 nW when on-call waiting for IoT events. Second, the proposed clock-free multi-function detectors with offline and online programmability are able to character the signal features of versatile IoTs events and allow versatile and dynamic wake-up functions. Third, the proposed asynchronous pipelined event-driven architecture minimizes the system activity and thus power, because a power-hungry high-performance system (HPS) is only woken up when a detected parameter crosses its corresponding threshold. As such, the long-term average power (LTA-power) is dominated by the always-on circuits in RSE scenarios. The measurement results achieve 71–75 nW for three typical applications, i.e., heart rate, epilepsy, and keyword envelope detection. The LTA power is only 57 nW when waiting for RSE events, which is 30 $\times $ lower than a prior general-purpose wake-up chip. Compared with other works of dedicated voice and acoustic wake-up functions, this work consumes 2 $\times $ and 17 $\times $ less power, respectively, while featuring 16 $\times $ higher signal bandwidth and a broader versatility.

This article introduces a high-voltage (HV) compliant, energy-efficient current-mode stimulator featuring a proposed boost-based dynamic voltage supply (DVS) to minimize the voltage dropout. The stimulator employs an activate-on-demand asynchronous strategy, instructing the boost converter to generate the dynamically increased high voltage that tracks the electrode’s voltage drop, thus achieving a near-adiabatic stimulation. The strategy relies on measuring the boost’s varying voltage conversion ratio (VCR), which is facilitated by an 8-bit voltage ratio quantizer (VRQ) proposed in this article. Furthermore, the boost converter employs a low-power, fast-speed, HV gate driver (HVGD) to control its p-type power switch that connects the inductor to the HV output. This article also presents a dedicated digital circuit that generates the pulse signals for controlling the n-type power switch and the HVGD. This digital circuit is driven by a five-phase clock from a current-starved ring oscillator. A highly efficient rotationally symmetric level shifter is utilized for the ring oscillator’s output, translating its level and improving its rise/fall time. The boost converter reaches a peak efficiency of 90.2%, enabling the stimulator to achieve an end-to-end energy efficiency of up to 86% during a biphasic stimulation of 6 mA. The stimulator IC, fabricated using 0.18-m bipolar–CMOS–DMOS (BCD) technology, occupies a compact area of 2.16 mm ² . It exhibits low static power consumption at 1.78 W, promising battery-powered implants with an extended lifetime and a reduced form factor.

Multi-level cell (MLC) ferroelectric FETs (FeFETs) face critical reliability challenges including variation, endurance and write disturb. In this work, we proposed an innovative solution to tackle all the three challenges within a compact writing scheme. Combining error correction, endurance recovery, and self-compensated writing, the proposed scheme achieves a > 6× reduction in error ratio (ER), a > 100 improvement in endurance, and a > 7× reduction in Vth shift. Reliable 2 bits/cell storage with high endurance of 108 cycles and write-disturb immunity is experimentally demonstrated in the fabricated 1T FeFET array. This writing scheme is realized within a single work flow, and can be readily implemented in the operation circuits.

This paper presents an energy-efficient 15.7-V-compliant current-mode stimulator with a proposed boost-based dynamic voltage supply that minimizes the stimulator’s voltage dropout. The boost uses a proposed 8-bit quantizer that measures the voltage ratio of its output to the input to digitally achieve the discontinuous conduction mode (DCM). A low-power high-voltage gate driver with a short switching transient time is proposed to improve energy efficiency. The converter achieves 90.2% peak efficiency, and up to 86% end-to-end energy efficiency is realized when a 6-mA biphasic stimulation is carried out. The stimulation IC is fabricated in 0.18 $\mu$m Bipolar-CMOS-DMOS (BCD) technology and occupies an area of 2.16 m$\mathrm{m}^{2}$. This stimulator consumes a low static power of 1.78 $\mu$W, promising battery-powered implants with a long lifetime and a small form factor.