This article introduces a high-voltage (HV) compliant, energy-efficient current-mode stimulator featuring a proposed boost-based dynamic voltage supply (DVS) to minimize the voltage dropout. The stimulator employs an activate-on-demand asynchronous strategy, instructing the boost converter to generate the dynamically increased high voltage that tracks the electrode’s voltage drop, thus achieving a near-adiabatic stimulation. The strategy relies on measuring the boost’s varying voltage conversion ratio (VCR), which is facilitated by an 8-bit voltage ratio quantizer (VRQ) proposed in this article. Furthermore, the boost converter employs a low-power, fast-speed, HV gate driver (HVGD) to control its p-type power switch that connects the inductor to the HV output. This article also presents a dedicated digital circuit that generates the pulse signals for controlling the n-type power switch and the HVGD. This digital circuit is driven by a five-phase clock from a current-starved ring oscillator. A highly efficient rotationally symmetric level shifter is utilized for the ring oscillator’s output, translating its level and improving its rise/fall time. The boost converter reaches a peak efficiency of 90.2%, enabling the stimulator to achieve an end-to-end energy efficiency of up to 86% during a biphasic stimulation of 6 mA. The stimulator IC, fabricated using 0.18-m bipolar–CMOS–DMOS (BCD) technology, occupies a compact area of 2.16 mm ² . It exhibits low static power consumption at 1.78 W, promising battery-powered implants with an extended lifetime and a reduced form factor.

This brief presents a low-power, high-precision neural recording circuit for closed-loop deep brain stimulation (DBS). It adopts a switched-capacitor (SC) low-pass filter (LPF) with the double sampling technique to efficiently attenuate high-frequency noise and signal with precise cut-off frequency. To improve power efficiency, this brief proposes a multi-sampling successive approximation register (SAR) analog-to-digital converter (ADC) for quantization. It synchronously samples LPF’s output, thus maximizing LPF’s power utilization. The singlechannel prototype chip was fabricated in a 180 nm CMOS process. The neural recording channel consumes 31.98 μ W from a 1.8-V supply. The proposed 11-bit multi-sampling SAR ADC features an ENOB of 10.38 bits at a sampling rate of 20.83 kS/s. The measured input-referred noise of the neural recording channel is 1.52 μ Vrms for 1 Hz-300 Hz band and 1.96 μ Vrms for 300 Hz-6.5 kHz band, respectively, promising a high precision for neural recording in closed-loop DBS systems.