Modern day hardware design is heavily focused on software simulations and verification. ASIC design is complex, and its abstraction may lead to losing motivation to develop knowledge and skills in the field. It is also very costly and inaccessible outside the industry, especially on a larger scale. FPGAs are devices which are affordable and allow unexperienced people, like students, to have an accessible and observable starting point in hardware development. On the other hand, protocol standards and devices nowadays are so complex that one will need to spend years to understand and feel comfortable dealing with corporate methodologies, environments and development process. One of the still evolving, recently developed ISA for example, RISC-V, is a broad area to learn. Often the fastest and in-depth way to learn is by observation, getting familiar with accessible yet challenging design and making modifications to and experimenting with such platforms.

Preserving critical data, preventing unauthorized access, securing communication are aspects of information security. To implement them as hardware is more reliable than software. There are various hardware solutions that suggest using a separate computational unit which is capable of providing various security enhancements. This article describes a heterogeneous security architecture with a tightly coupled security core to the CPU. A security interface that allows direct control and monitory of the security core over the CPU is proposed. In the article analysis of how the interface interacts with the controlled and monitored CPU is done. This analysis explains the benefits and why for certain aspects control is implemented seeking performance while for others - using less logic.

Preserving critical data, preventing unauthorized access, and securing communication are aspects of information security. Implementing them as hardware is more reliable than software. There are various hardware solutions that suggest using a separate computational unit, which is capable of providing various security enhancements. This article describes a heterogeneous security architecture with a tightly coupled security core to the CPU. A security interface that allows direct control and monitoring of the security core over the CPU is proposed. In the article analysis of how the interface interacts with the controlled and monitored CPU is done. This analysis explains the benefits and why for certain aspects, control is implemented seeking performance, while for others, using less logic.