With the rapid development of Internet technology, information security has become increasingly important. Cryptographic analysis techniques, especially side-channel analysis (SCA), pose a significant threat to security systems. The latest SCA technology mainly utilizes the physical leakage signals generated during the operation of encryption devices, such as power consumption, temperature and electromagnetic radiation. These signals themselves carry the physical characteristics of the device, which are related to the encryption algorithm. Among them, the power consumption trace remains the main target of modern SCA research. However, such trajectories often bring about some analytical difficulties, such as the data sequence being too long, the feature points being distributed sparsely, and the internal relationships of the data being complex. These challenges hinder effective analysis. While Transformer architectures are good at capturing long-range dependencies in sequential data, their high computational complexity limits practical deployment. To address this, we propose replacing the self-attention (SA) module in Transformers with a focal modulation module. This modification significantly reduces computational complexity and reduces computational operations during feature extraction, enabling efficient and accurate side-channel attacks. Experimental results on benchmark datasets (ASCAD, AES_RD, AES_HD, DPAv4) demonstrate the superiority of our approach. The proposed method achieves a reduction in training time compared to standard Transformer models, and achieves superior key recovery performance, outperforming existing state-of-the-art models.

The application of deep learning in side-channel analysis faces critical challenges arising from dispersed public datasets—i.e., datasets collected from heterogeneous sources and platforms with varying formats, labeling schemes, and sampling settings—and insufficient sample distribution uniformity, characterized by imbalanced class distributions and long-tailed label samples. This paper presents a systematic analysis of symmetric cryptographic AES side-channel leakage datasets, examining how these issues impact the performance of deep learning-based side-channel analysis (DL-SCA) models. We analyze over 10 widely used datasets, including DPA Contest and ASCAD, and highlight key inconsistencies via visualization, statistical metrics, and model performance evaluations. For instance, the DPA_v4 dataset exhibits extreme label imbalance with a long-tailed distribution, while the ASCAD datasets demonstrate missing leakage features. Experiments conducted using CNN and Transformer models show that such imbalances lead to high accuracy for a few labels (e.g., label 14 in DPA_v4) but also extremely poor accuracy (<0.5%) for others, severely degrading generalization. We propose targeted improvements through enhanced data collection protocols, training strategies, and feature alignment techniques. Our findings emphasize that constructing balanced datasets covering the full key space is vital to achieving robust and generalizable DL-SCA performance. This work contributes both empirical insights and methodological guidance for standardizing the design of side-channel datasets.

Field-programmable gate arrays (FPGAs) have garnered considerable interest and utilization, largely owing to their inherent flexibility and customizability. In this context, electronic design automation (EDA) technology serves as an instrumental facilitator for FPGA applications. Nevertheless, the emergence of hardware Trojans (HTs) represents a major vulnerability in FPGA security. To mitigate the risks associated with hardware Trojans, a formula has been devised to compute the controllability and observability of each signal within logic units in look-up table (LUT) netlists. Subsequently, a security verification methodology aimed at HT detection within these LUT netlists has been developed and incorporated into the EDA tool, BFDS. Detailed procedural steps for HT detection, including interactions with the graphical user interface, are elucidated. The efficacy of this embedded HT detection tool is substantiated through experimental validation. The results from these experiments confirm the capacity of the tool to successfully identify Trojans at the LUT-level netlist while seamlessly integrating into EDA toolchains, thereby enhancing the security of future FPGA design endeavors.

This paper focuses on sorting out two backbone network variants’ development routes for CNNs and transformers based on deep learning methods for side-channel analysis. Combining parametric and quantitative structural analyses, it is preferred that improvement research be carried out on the structure of the continuation CNN variants. Firstly, the comparative reproduction of Zaid’s Efficient CNN and Wouters’ Simplified Efficient CNN will be carried out; second, ResNet will be designed and implemented based on residual structure and the improved design of feature-coded CNNs; finally, the four methods in DPA_ contest v4.1, AES_RD, AES_HD, and ASCAD public datasets will be used for extensive analysis experiments to explore the effects of six preprocessing roles at three scales and further explore the impact of data enhancement by dataset noise, offset, and amplitude scaling. The experimental results show that ResNet based on the residual structure and the coded feature CNN proposed in this paper exhibit better performance advantages than the previous methods. Preferring a preprocessing method for each dataset can continue to reduce the mean rank; continuing to overlay data enhancement methods can make the model easier to converge and increase the model’s generalization ability. To advance the research in the branch of CNNs and transformer variants in the SCA field, the model methods obtained from the above experiments and the datasets obtained from the processing have been made publicly available on GitHub.

SRAM-based FPGAs, with their flexible programmability and parallel execution features, have been widely used, and the security of such devices has drawn significant attention. Especially in the era of artificial intelligence, FPGA architectural optimizations and evolving application models have introduced novel security characteristics and threats. In this work, we introduce a taxonomy of FPGA threats and explore new threat features and potential countermeasures in the era of AI. We focus on evaluating the research trends of FPGA security, including both security threats and protection measures. Then, we propose a new perspective on the involvement of FPGA manufacturers in FPGA security and introduce the main security measures used in COTS FPGA products. Finally, we summarize the security challenges and offer future research directions.

With the widespread deployment of SRAM-based FPGAs across multiple application scenarios, the soft error resilience of FPGAs has become critically important. To mitigate errors, current mainstream techniques either incur significant PPA (Performance, Power, Area) overhead or exhibit inadequate fault tolerance. Addressing this fault-tolerance–PPA trade-off, this study reduces resource consumption in Triple Modular Redundancy (TMR) implementations while deploying high-efficiency hardening methods at alternative granularity tiers. We propose a multi-tier spatiotemporal hardening framework and evaluation method (MSHE-SE), achieving two key contributions on a 70-million-gate FPGA platform: full-flow, full-granularity protection from RTL to post-physical-implementation netlists by integrating spatiotemporal methods across multiple FPGA EDA stages; and dual-mode fault injection validation utilizing synergistic JTAG and SEM mechanisms. A pseudo-random sequence generator emulates real-world environments to evaluate the system Mean Time Between Failures (MTBF) of FPGA designs. Finally, experimental results demonstrate that, compared to commercial TMR tools, the proposed method reduces LUT resource utilization by 10.9–45.7% and enhances system MTBF by an average factor of 18.28×.