Aerospace-grade SRAM-based field-programmable gate arrays (FPGAs) used in space applications are highly susceptible to single event effects, leading to soft errors in FPGAs. Additionally, as FPGAs scale up, the difficulty of correcting soft errors also increases. This paper proposes that performing soft error sensitivity analysis on FPGAs can help target the more sensitive areas for detection and correction, thereby improving the efficiency of soft error repair. Firstly, in accordance with the dual-layer architecture of SRAM-based FPGAs, methods for the soft error sensitivity analysis of FPGA application layer resources and configuration bitstreams are reviewed. Subsequently, based on the analysis results, it also covers corresponding application layer memory scrubbing and configuration scrubbing techniques. A prospective look at emerging soft error mitigation technologies is discussed at the end of this review, supporting the development of highly reliable aerospace-grade SRAM-based FPGAs.

Memory used for storing the configuration bitstream of field programmable gate array in space applications often encounters single event upset problems, which may disrupt the integrity of data in memory and lead to unpredictable failures. For commercial memories used in low Earth orbit (LEO), single-bit errors and double-byte errors account for a large proportion. Meanwhile, error detection and correction (EDAC) schemes, e.g., triple modular redundancy, linear block codes, memory scrubbing, and the combination of these schemes, are very popular in LEO missions. To further these works, a novel EDAC scheme with cascaded “Bose–Chaudhuri–Hocquenghem and cyclic redundancy check” codes and a proper scrubbing method is presented in this paper. The performance of the proposed design is measured and compared with state-of-the-art EDAC schemes in terms of hardware overhead, time overhead and error correction and detection capabilities. It is concluded that the proposed EDAC scheme is better suited for memory in space applications.

With the decreasing size of manufacturing process, the scale of island-style field programmable gate array (FPGA) becomes larger, which leads to the increasing complexity of FPGA routing resources, especially hex programmable interconnect points (PIPs). Hex PIPs which span six tiles of the island-style FPGA have complex interconnect rules. Accordingly, research on complete hex PIPs test is rarely involved in the study of routing resources test. Therefore, this paper analyzes the hex PIPs architecture of the island-style FPGA, summarizes the interconnect rules of the hex PIPs mathematically in a two-dimensional coordinate system, and presents two proper test algorithms at the same time. The hex PIPs are divided into three directions, that is, horizontal, vertical, and oblique. According to the proposed coordinate equations, a cycle test structure in the horizontal and vertical directions and a test structure with partial-cascade patterns in the oblique direction are designed respectively. It is concluded that the proposed methods can achieve 100% fault coverage for the hex PIPs test in all directions, and the configuration number for hex lines test with the same methods is significantly decreased than previous researches.

SRAM-based FPGAs, with their flexible programmability and parallel execution features, have been widely used, and the security of such devices has drawn significant attention. Especially in the era of artificial intelligence, FPGA architectural optimizations and evolving application models have introduced novel security characteristics and threats. In this work, we introduce a taxonomy of FPGA threats and explore new threat features and potential countermeasures in the era of AI. We focus on evaluating the research trends of FPGA security, including both security threats and protection measures. Then, we propose a new perspective on the involvement of FPGA manufacturers in FPGA security and introduce the main security measures used in COTS FPGA products. Finally, we summarize the security challenges and offer future research directions.

A new magnetic integrated parallel current sharing control method for parallel silicon carbide (SiC) power devices is presented in this article. The problem of the application of parallel connected SiC power devices is analyzed. The coupled inductance method is adopted to solve the problem. Based on the active-back converter, we establish the theoretical model of the coupled inductance, and figure out its working mechanism. The integrated magnetic device is designed based on the working mechanism, and the effectiveness is determined through simulation. A 12 V/10 A output magnetic integrated active-flyback converter prototype is fabricated and tested to verify the strategy. Measurement results show that, with the proposed magnetic integrated method, the mismatch voltage is suppressed to 0.1 V under all load conditions, and the efficiency increases by at most 6.52% under full load conditions.

Deep learning (DL) models have achieved remarkable progress in natural language processing, computer vision, content generation, and edge intelligence; however, their rapidly increasing computational complexity, memory demand, and deployment diversity pose significant challenges for practical implementation. Field-programmable gate arrays (FPGAs) provide customized low-precision computation, spatial dataflow, on-chip data reuse, reconfigurability, and rich I/O capabilities, making them an important platform for DL inference. This paper presents a systematic review of FPGA-based DL deployment from a cross-layer perspective spanning model, compiler, architecture, runtime, and electronic design automation (EDA). Following a PRISMA-guided evidence synthesis protocol, this review analyzes DL workload characteristics, FPGA architectural optimizations, deployment toolflows, and physical implementation challenges. A unified taxonomy is proposed along the specialization–programmability continuum, including model-fixed accelerators, generator-based accelerators, template-configurable accelerators, and ISA-programmable overlays. These approaches are compared according to hardware regeneration requirements, model adaptability, operator coverage, compilation cost, and deployment flexibility. Furthermore, emerging workloads, including vision Transformers, graph neural networks, large language models, and multimodal models, are analyzed from the perspectives of computation, memory behavior, and runtime coordination. The review shows that FPGA deployment efficiency increasingly depends on memory capacity, mutable state management, operator support, and end-to-end compilation capability rather than peak multiply–accumulate throughput alone. Based on the analysis of 70 primary FPGA implementation studies, this paper highlights that reliable cross-study comparison requires careful consideration of model configuration, precision, execution phase, batch size, memory residency, FPGA platform, and evidence maturity. For multimodal generative models, the current evidence remains limited, with no identified end-to-end FPGA-based vision–language model implementation in the reviewed corpus. This review provides a systematic perspective for future FPGA-based DL deployment research, emphasizing cross-layer optimization, physically aware compilation, extensible accelerator architectures, and practical deployment efficiency.