With the widespread deployment of SRAM-based FPGAs across multiple application scenarios, the soft error resilience of FPGAs has become critically important. To mitigate errors, current mainstream techniques either incur significant PPA (Performance, Power, Area) overhead or exhibit inadequate fault tolerance. Addressing this fault-tolerance–PPA trade-off, this study reduces resource consumption in Triple Modular Redundancy (TMR) implementations while deploying high-efficiency hardening methods at alternative granularity tiers. We propose a multi-tier spatiotemporal hardening framework and evaluation method (MSHE-SE), achieving two key contributions on a 70-million-gate FPGA platform: full-flow, full-granularity protection from RTL to post-physical-implementation netlists by integrating spatiotemporal methods across multiple FPGA EDA stages; and dual-mode fault injection validation utilizing synergistic JTAG and SEM mechanisms. A pseudo-random sequence generator emulates real-world environments to evaluate the system Mean Time Between Failures (MTBF) of FPGA designs. Finally, experimental results demonstrate that, compared to commercial TMR tools, the proposed method reduces LUT resource utilization by 10.9–45.7% and enhances system MTBF by an average factor of 18.28×.

Selecting a routing architecture for Embedded FPGAs (eFPGAs) is expensive because candidate quality normally becomes available only after physical implementation. We formulate this task as a decision across information stages under a verification budget of five candidates and compare information obtained from prior evaluations, placement, and early routing. Across 52 circuits from five application domains, history-only H0 achieves 82.69% coverage when retaining five candidates under a 3% area-delay product tolerance without implementing any target candidate. Placement information at P0 reaches 82.05% and provides no confirmed improvement. RT1 incorporates the routing state recorded at the first PathFinder iteration and raises coverage to 96.15%, a confirmed gain of 14.10 percentage points over P0. A matched ScalarOnly ablation shows that both model representations benefit from this response, while StageRank retains the exact optimum more often at RT1. Together, these results demonstrate that the proposed framework combines reusable historical knowledge, graph representations, and early physical observations to support systematic and efficient eFPGA architecture exploration. Historical evaluations provide a strong basis for initial selection across circuits, while information from the target circuit adds confirmed value only after the interaction between circuit and architecture becomes observable. RT1 is the earliest stage evaluated to provide this information and is therefore selected as the fixed stage under the evaluated protocol.

Deep learning (DL) models have achieved remarkable progress in natural language processing, computer vision, content generation, and edge intelligence; however, their rapidly increasing computational complexity, memory demand, and deployment diversity pose significant challenges for practical implementation. Field-programmable gate arrays (FPGAs) provide customized low-precision computation, spatial dataflow, on-chip data reuse, reconfigurability, and rich I/O capabilities, making them an important platform for DL inference. This paper presents a systematic review of FPGA-based DL deployment from a cross-layer perspective spanning model, compiler, architecture, runtime, and electronic design automation (EDA). Following a PRISMA-guided evidence synthesis protocol, this review analyzes DL workload characteristics, FPGA architectural optimizations, deployment toolflows, and physical implementation challenges. A unified taxonomy is proposed along the specialization–programmability continuum, including model-fixed accelerators, generator-based accelerators, template-configurable accelerators, and ISA-programmable overlays. These approaches are compared according to hardware regeneration requirements, model adaptability, operator coverage, compilation cost, and deployment flexibility. Furthermore, emerging workloads, including vision Transformers, graph neural networks, large language models, and multimodal models, are analyzed from the perspectives of computation, memory behavior, and runtime coordination. The review shows that FPGA deployment efficiency increasingly depends on memory capacity, mutable state management, operator support, and end-to-end compilation capability rather than peak multiply–accumulate throughput alone. Based on the analysis of 70 primary FPGA implementation studies, this paper highlights that reliable cross-study comparison requires careful consideration of model configuration, precision, execution phase, batch size, memory residency, FPGA platform, and evidence maturity. For multimodal generative models, the current evidence remains limited, with no identified end-to-end FPGA-based vision–language model implementation in the reviewed corpus. This review provides a systematic perspective for future FPGA-based DL deployment research, emphasizing cross-layer optimization, physically aware compilation, extensible accelerator architectures, and practical deployment efficiency.