Advanced 3-D synaptic devices with a stackable and-type rounded dual channel (RDC) flash memory structure are proposed for neuromorphic networks. and synaptic arrays composed of RDC flash devices enable program/erase (PGM/ERS) using Fowler-Nordheim (FN) tunneling, high-speed operation because of parallel read operations, and high density with multilayer stacking. Key fabrication steps are explained and the successful operation of the device in 3-D stacked structure is verified by measurement results. In addition, current summation and selective PGM/ERS behavior in synaptic arrays, which are essential in neuromorphic networks, are demonstrated. A hardware-based convolutional neural network (CNN) is designed considering the operating characteristics of the RDC flash memory. The accuracy evaluation and analysis for the CIFAR-10 image classification are performed. In addition, we propose a method of constructing a hardware-based CNN with the high-density synaptic array by stacking layers.

Validation methods for hard real-time jobs are usually performed based on the maximum execution time. The actual execution time of jobs are assumed to be known only when the jobs arrive or not known until they finish. A predictable algorithm must guarantee that it can generate a schedule for any set of jobs such that the finish time for the actual execution time is no later than the finish time for the maximum execution time. It is known that any job-level fixed priority algorithm (such as Earliest Deadline First) is predictable. However, job-level dynamic priority algorithms (such as Least Laxity First) may or may not. In this paper, we investigate the predictability of a job-level dynamic priority algorithm EDZL (Earliest Deadline Zero Laxity). We show that EDZL is predictable on the domain of integers regardless of the knowledge of the actual execution times. Based on this result, furthermore, we also show that EDZL can successfully schedule any periodic task set if the total utilization is not greater than (m + 1)/2, where m is the number of processors.

An AND-type flash synaptic array is cointegrated with CMOS circuits using a novel fabrication method. Electrical characteristics of the basic circuit blocks required for neural network operation are verified. By reducing the number of masks and fabrication steps required, the proposed fabrication method successfully integrates synaptic array and CMOS peripheral circuits, including integrate-and-fire (I&F) circuits and passive devices, on a single wafer. The proposed fabrication method provides a methodology for the efficient implementation of hardware-based neural networks as well as verification of excellent compatibility of the proposed synaptic array with CMOS technology.

A new SPICE model for vertical NAND (VNAND) flash memory cells is proposed based on the BSIM-CMG model and a modified mobility equation using the Meyer–Neldel (MN) rule. Unlike in previous models, the average and standard deviation of the subthreshold swing (SS), threshold voltage ( $\textit{V}_{\text{th}}$ ), maximum transconductance ( $\textit{g}_{\text{m,max}}$ ), maximum word-line (WL) voltage ( $\textit{V}_{\text{WL,max}}$ ), and maximum bitline (BL) current ( $\textit{I}_{\text{max}}$ ) of WL cells at various positions are accurately modeled over the full BL/WL bias range. The step response in transient SPICE simulation agrees very well with a calibrated Technology Computer Aided Design (TCAD) model. Also, a new compact model that predicts $\textit{V}_{\text{th}}$ change during program/erase (PGM/ERS) operation is proposed and validated. The model is expected to be beneficial for analog applications, such as synaptic devices in neural networks.

A gated diode with a charge trap insulator stack (Al ₂ O ₃ /Si ₃ N ₄ /SiO ₂ ) is proposed as a synaptic device and its potentiation and depression operations have been demonstrated. Using the band-to-band tunneling current, the gated diode operates with low current (in nanoampere range) and is suitable for low-power hardware-based neural networks. Since the proposed device has merits on simple and compact structure (half of a MOSFET) and compatibility with conventional CMOS technology, integration with CMOS peripheral circuits including neuron circuits and driving IC is possible.

On‐chip training of neural networks (NNs) is regarded as a promising training method for neuromorphic systems with analog synaptic devices. Herein, a novel on‐chip training method called direct gradient calculation (DGC) is proposed to substitute conventional backpropagation (BP). In this method, the gradients of a cost function with respect to the weights are calculated directly by sequentially applying a small temporal change to each weight and then measuring the change in cost value. DGC achieves a similar accuracy to that of BP while performing a handwritten digit classification task, validating its training feasibility. In particular, DGC can be applied to analog hardware‐based convolutional NNs (CNNs), which is considered to be a challenging task, enabling appropriate on‐chip training. A hybrid method is also proposed that efficiently combines DGC and BP for training CNNs, and the method achieves a similar accuracy to that of BP and DGC while enhancing the training speed. Furthermore, networks utilizing DGC maintain a higher level of accuracy than those using BP in the presence of variations in hardware (such as synaptic device conductance and neuron circuit component variations) while requiring fewer circuit components.