In high-power medium-voltage applications, inductors usually have multiple windings on a single core, due to the high inductance value and high current stress. The multiple coils are electronically connected in either series or parallel, with considerations of windings loss and cost. However, the differences in parasitic capacitance of inductors using parallel and series connections are not discussed. Therefore, this article reveals that in comparison to parallel connections for windings, utilizing series connection for winding can significantly reduce the parasitic capacitance in multiwindings inductors without sacrificing the power density and adding manufacturing complexities. Physics-based models of parasitic capacitance in inductors with round-cable and copper-foil windings are developed for theoretical analysis. According to the theoretical analysis, the equivalent capacitance contributed by the stored electric field energy between two layers can be halved at least. The theoretical analysis is also verified by FEM simulations. Six prototyped inductors are experimentally compared to validate the theory.

With the development of wide band-gap devices, Silicon Carbide (SiC) semiconductor devices in 10–15 kV voltage class offer potentials in medium-voltage (MV) systems. To ensure the reliable operation of these MV SiC devices, gate driver power supplies must meet specific requirements: MV isolation capability, low coupling capacitance, stable performance across fluctuating voltage potentials, and assembly convenience. This article proposes a customized gate driver power supply solution. The proposed core-series-coupling planar transformer meets the specified requirements and significantly reduces common-mode capacitance by series connection of core, while maintaining ease of manufacturing. In addition, the open-loop voltage regulator circuit model ensures precise output voltage by accounting for winding resistance and magnetizing inductance. This article presents an MV SiC gate driver that achieves a partial discharge inception voltage of 11.5 kV and the transformer exhibits a low coupling capacitance of 0.42 pF. Additionally, this article conducts a 6 kV/30 A double pulse test, demonstrating the robust performance of the gate driver even at switching speeds of 133.9 V/ns during turn-off and 111.6 V/ns during turn-on transients.

This paper investigates the effects of airgaps between different parts of magnetic cores on the parasitic capacitance of magnetic components, which was excluded by previous research. According to the physical mechanism of the electric field in airgaps, the single-perfect-electric-conductor assumption, which has been widely used in previous research, is improved to muti-perfect-electric-conductor assumption by considering the effects of airgaps on the voltage potential distribution of magnetic components. Furthermore, the improved physics-based analytical model is developed based on the proposed assumption for demonstrating the effects of airgaps on the parasitic capacitance of magnetic components. The analyses are verified by finite-element-method simulations and experimental verifications, which accurately predict the effects of airgaps on the voltage potential distribution and the parasitic capacitance in magnetic components.

Parasitic capacitances are important in magnetic components, especially for the high-frequency power electronic converters enabled by wide-bandgap semiconductors. For the clearer and more structural understanding of parasitic capacitance in magnetic components, this paper provides a comprehensive compendium of parasitic capacitance including the definition, quantification, and modelling. Different types of parasitic capacitances based on intrinsic properties are defined with corresponding frequency ranges of interest. Both frequency-domain and time-domain measurement methods are introduced for more accurate and convincing quantification. As for the physical mechanism and modelling of parasitic capacitances, energy-based, transmission-line, and behaviour-based approaches are discussed. In the end, the challenges and perspectives are provided for further inspirations.

With a higher penetration of electric vehicles (EVs), the demands to accommodate a wide range of battery voltages by DC fast-charging station are increasing. It is crucial to design converters able to provide the required power as efficiently as possible. A proposed topology to accommodate the wide voltage range of EVs, the four-phase current-fed push-pull converter, is investigated in this work. An interleaved optimization algorithm is developed to optimize the fixed converter components, and variable control parameters. Modifications to the converter topology are implemented to increase the efficiency and reduce the number of magnetic components and semiconductors in the converter.