Recent developments within the field of medium voltage wide-bandgap semiconductor devices are drawing attention from both researchers and industries due to the demanding requirements for more efficient high-power energy conversion. The rapid development has entailed an increased awareness of the negative impact of the increased rate of change in voltage, d v /d t , and its derived issues caused by the inevitable parasitic capacitive couplings. This article is dedicated to present an overview of the parasitic capacitive couplings in high-power medium voltage power electronic converter systems, using an example reference system enabled by medium voltage SiC mosfet s. The definitions of capacitive couplings are presented and the impacts raised by parasitic capacitive couplings are reviewed. In addition, the similarities of different capacitive couplings introduced by components in practical medium voltage systems are presented and summarized. Lastly, the challenges and future work with respect to parasitic capacitive couplings in medium voltage power electronics converter systems are shared from the authors' perspective.

In order to guide the parameters design of voltage-mode controlled switching dc-dc converter, taking continuous conduction mode (CCM) buck converter as an example, the discrete iterative-map model for six possible evolutions is established. Based on which, the dynamical behaviors of different pulse-width modulation (PWM) parameters on voltage-mode controlled buck converter are revealed via bifurcation diagrams. In addition, the closed-loop z-domain transfer function and the corresponding stability boundary equations are derived. Meanwhile, the operating regions with varying circuit parameters for different PWM methods can be estimated and divided by the boundary equations, which can provide guidance for stability control. The research results indicate the nonlinear phenomena, such as period window, Hopf bifurcation, period-doubling bifurcation, chaos and so on, exist in the voltage-mode controlled buck converter. Dual-edge modulation (symmetrical dual-edge or asymmetrical dual-edge) shows more stable performance than single-edge modulation (leading-edge or trailing-edge) under certain circuit parameters. Moreover, there are two similar but different Hopf bifurcation phenomena in the voltage-mode controlled buck converter. The existence and difference of them are theoretically analyzed by eigenvalues and Poincare sections. Finally, simulation waveforms and experimental results are given to verify the theoretical analysis.

With the development of wide band-gap devices, Silicon Carbide (SiC) semiconductor devices in 10–15 kV voltage class offer potentials in medium-voltage (MV) systems. To ensure the reliable operation of these MV SiC devices, gate driver power supplies must meet specific requirements: MV isolation capability, low coupling capacitance, stable performance across fluctuating voltage potentials, and assembly convenience. This article proposes a customized gate driver power supply solution. The proposed core-series-coupling planar transformer meets the specified requirements and significantly reduces common-mode capacitance by series connection of core, while maintaining ease of manufacturing. In addition, the open-loop voltage regulator circuit model ensures precise output voltage by accounting for winding resistance and magnetizing inductance. This article presents an MV SiC gate driver that achieves a partial discharge inception voltage of 11.5 kV and the transformer exhibits a low coupling capacitance of 0.42 pF. Additionally, this article conducts a 6 kV/30 A double pulse test, demonstrating the robust performance of the gate driver even at switching speeds of 133.9 V/ns during turn-off and 111.6 V/ns during turn-on transients.

Gate oscillations exist in paralleled SiC MOSFETs, which can cause false switching behavior and device damage. This article investigates gate oscillations in paralleled 10 kV SiC mosfets as it is currently one of the bottlenecks for paralleling. During the switching transient, the paralleled SiC mosfets operate in their saturation region, where a closed-loop feedback system is formed between the mosfet transconductance and the parasitic distributions in the circuit. The instability of the closed-loop feedback system is key in describing the gate oscillation mechanism. Therefore, a small signal circuit model of two parallel 10 kV SiC mosfets is used to analyze this mechanism, which takes into account both the parasitic inductances and capacitances of the mosfet, power module, and external connections to predict the impact of different parasitic parameters. From the circuit model, four methods are proposed to mitigate the gate oscillations. Finally, experiments are conducted in a double pulse test platform at 6 kV/20 A, showing a good prediction of the gate oscillations and significant damping by the proposed methods.

It is commonly assumed that power semiconductor switching losses are the same for high-side and low-side devices in a half-bridge power module. However, this article reveals that the high-side SiC mosfet in a medium-voltage power module exhibits over 40% higher switching energy compared with the low-side SiC mosfet . The loss imbalance is attributed to the parasitic high-side gate capacitance in the power module, which contributes to the equivalent high-side Miller capacitance. A physics-based switching energy dissipation model is, therefore, proposed, distinguishing between low-side and high-side switching energy dissipation. Double pulse testing demonstrates that high-side switching energy dissipation increases by 5 mJ per 2.5-pF increment in the equivalent Miller capacitance, aligning closely with the analytically calculated increase of 6 mJ per 2.5 pF. Continuous power module testing shows a 10 $\mathrm{^{\circ }}$ C increase in high-side junction temperature. The findings from this article offer crucial insights into research, design, and manufacturing of half-bridge modules enabled by SiC mosfet s.

Hybrid conduction mode (HCM) is gradually applied in single-inductor dual-output (SIDO) dc-dc converter as its advantages of reducing switching loss and minimizing cross-regulation. However, it shows that the circuit parameters will affect the stability and restrict its operation range, which causes the converter to operate in non-HCM and these advantages are lost. In this paper, to figure out this phenomenon, eight different operation modes of the HCM SIDO buck converter are analyzed. On this basis, a three-dimensional discrete-time model, which is suitable for variable-frequency control, is established. And then, the effect of output capacitors and its equivalent series resistances (ESRs), load resistors, input voltage and output voltages, constant turn-off time on the stability is discussed. The study results show that the stability and operation mode is sensitive to the difference circuit parameters and control parameters. In addition, the dynamic ramp-compensation based on inductor current is proposed and analyzed for stabilization control, which can broaden the stable operation range of this converter. Finally, experimental results validate the accuracy of proposed theoretical analysis.