This paper presents a design of a variation-resilient and energy-efficient ternary memory cell (TSRAM) suited for power-demanding IoT applications that run on batteries. The TSRAM cell utilizes a latch composed of an efficient ternary buffer (TBUF) with positive feedback, a single-bitline, and a transmission gate for switching access, with an overall area only about 39% more than binary 6T SRAM. The threshold voltage (V_th) tuning of CNTFET devices has been explored to achieve the three storage levels. Simulations were conducted using the Standard 32-nm CNTFET model file in the Synopsis HSPICE simulator. The projected design offers substantial reductions of 54.94% in read power, 67.06% in write power, and 21.59% in area compared to the best buffer-based TSRAM designs. These power savings are achieved by minimizing the transistor count and eliminating any direct current path between VDD and ground in the TBUF design for getting logic ‘1’. Furthermore, the proposed design demonstrates the highest logic ‘1’ static noise margin (SNM1) and shows resilience to process, voltage, and temperature (PVT) variations. The TSRAM electrical quality matrix (TEQM), a crucial figure of merit, indicates the superior performance of the proposed design for IoT applications. The study was further extended to conduct simulations and report the performance metrics of the proposed TSRAM array. Ultimately, to evaluate the real-world application of the triple memory structures, the pixel-by-pixel storage process of a grayscale image with three-value data content is performed based on a hardware algorithm. The obtained results demonstrate that the proposed TSRAM architecture has about a 26.3% improvement in hardware performance compared to its highest performing counterpart scheme.

This paper introduces a novel 10T SRAM cell optimized for low-power, high-reliability biomedical wearable systems. The proposed design features a read-assist mechanism to suppress read disturbs, enhancing read static noise margin (RSNM), while a decoupled pull-down path for the ‘0’ storage node improves write SNM (WSNM). Leveraging Stanford CNTFET models, HSPICE simulations reveal a 1.12× and 14.02× enhancement in RSNM and WSNM, respectively, at 0.3V over the conventional 6T cell. Additionally, the design achieves substantial power savings—3.02× (read), 1.97× (write), and 1.89× (leakage)—compared to state-of-the-art 9T/10T CNTFET SRAMs. Monte Carlo analysis further demonstrates superior robustness, with 2.38× and 6.62× higher yield in RSNM and WSNM at 0.3V, validating its reliability for energy-constrained biomedical applications.

This study proposes a high-performance β -Ga ₂ O ₃ trench-gate (TG) MOSFET employing a variable lateral doping (VLD) scheme to strengthen power-device capability. The analysis examines the impact of VLD engineering, high-κ HfO ₂ and Al ₂ O ₃ dielectrics, and field-plate structures on the electrical, thermal, and radio-frequency (RF) characteristics. HfO ₂ demonstrates lower ON-resistance and higher transconductance than Al ₂ O ₃ , along with reduced temperature sensitivity. The β -Ga ₂ O ₃ TG-MOSFET achieves picosecond-scale switching, with a turn-on delay of 31.6 ps and rise time of 33.2 ps, supported by low parasitic capacitances (C _iss = 126.1 fF mm ⁻¹ , C _rss = 89.5 fF mm ⁻¹ ). The turn-off transition (t _d(off) = 1.2 ns, t _f = 7.7 ns) confirms suitability for high-frequency power and RF operation. Incorporating dual field plates raises the off-state breakdown voltage from 2058 V to 3045 V an increase of 48% by lowering peak electric fields and redistributing the lateral field profile. The results confirm that the synergy between trench-gate design, lateral doping engineering, and dielectric optimization in β -Ga ₂ O ₃ markedly enhances switching behavior, heat management, and breakdown strength, making the proposed architecture a compelling solution for advanced high-power, high-temperature, and RF applications.