This paper presents a design of a variation-resilient and energy-efficient ternary memory cell (TSRAM) suited for power-demanding IoT applications that run on batteries. The TSRAM cell utilizes a latch composed of an efficient ternary buffer (TBUF) with positive feedback, a single-bitline, and a transmission gate for switching access, with an overall area only about 39% more than binary 6T SRAM. The threshold voltage (V_th) tuning of CNTFET devices has been explored to achieve the three storage levels. Simulations were conducted using the Standard 32-nm CNTFET model file in the Synopsis HSPICE simulator. The projected design offers substantial reductions of 54.94% in read power, 67.06% in write power, and 21.59% in area compared to the best buffer-based TSRAM designs. These power savings are achieved by minimizing the transistor count and eliminating any direct current path between VDD and ground in the TBUF design for getting logic ‘1’. Furthermore, the proposed design demonstrates the highest logic ‘1’ static noise margin (SNM1) and shows resilience to process, voltage, and temperature (PVT) variations. The TSRAM electrical quality matrix (TEQM), a crucial figure of merit, indicates the superior performance of the proposed design for IoT applications. The study was further extended to conduct simulations and report the performance metrics of the proposed TSRAM array. Ultimately, to evaluate the real-world application of the triple memory structures, the pixel-by-pixel storage process of a grayscale image with three-value data content is performed based on a hardware algorithm. The obtained results demonstrate that the proposed TSRAM architecture has about a 26.3% improvement in hardware performance compared to its highest performing counterpart scheme.

A Rectangular core-shell (RCS) is analyzed on vertically stacked gate oxide junctionless nanosheet along with doping and gate/dielectric engineering. This paper also proposes an N-type three fins vertically stacked with gate oxide stack junctionless nanosheet with opposite core doping in the channel known as RCS. The simulation results show that gate oxide stack with RCS junctionless nanosheet exhibit reduced I _OFF is 6.913E-21, increased I _ON is 2.408E-07, I _ON / I _OFF ratio is 0.418 x 10 ⁶ , DIBL is 6.9mV and SS of 60.65 mV/dec respectively. The core shell width variations with various gate oxide dielectric towards better I _ON , I _OFF and I _ON / I _OFF is analyzed. Interestingly, it is noted that for smaller shell thickness, the thickness of core should be equivalent to shell thickness and for larger shell thickness, thicker core is required. The device robustness towards analog and RF metrics are also evaluated with varied gate dielectrics. It has been observed that RCS architecture with opposite doping with HfO ₂ as gate oxide material has given outstanding outcomes compared to other gate oxide materials and without RCS method. Further, simulated the P-type of three fins vertically stacked with gate oxide stack junctionless nanosheet and combined both N-type and P-type three fins vertically stacked with gate oxide stack junctionless nanosheet to construct the CMOS inverter circuit. The voltage transfer characteristics (VTC) characteristics of junctionless nanosheet with RCS having HfO ₂ as gate-oxide based inverter has been notably improved as compared to the SiO ₂ , Al ₂ O ₃ and conventional three fins vertically stacked with gate oxide stack junctionless nanosheet inverter.

This paper introduces a novel 10T SRAM cell optimized for low-power, high-reliability biomedical wearable systems. The proposed design features a read-assist mechanism to suppress read disturbs, enhancing read static noise margin (RSNM), while a decoupled pull-down path for the ‘0’ storage node improves write SNM (WSNM). Leveraging Stanford CNTFET models, HSPICE simulations reveal a 1.12× and 14.02× enhancement in RSNM and WSNM, respectively, at 0.3V over the conventional 6T cell. Additionally, the design achieves substantial power savings—3.02× (read), 1.97× (write), and 1.89× (leakage)—compared to state-of-the-art 9T/10T CNTFET SRAMs. Monte Carlo analysis further demonstrates superior robustness, with 2.38× and 6.62× higher yield in RSNM and WSNM at 0.3V, validating its reliability for energy-constrained biomedical applications.

In this work, we report the RF/DC performance of novel AlN/GaN/Graded-AlGaN/GaN double-channel HEMT (AlN-GDC-HEMT) on SiC wafer for the first time. The study compares the performance between conventional AlGaN/GaN/Graded-AlGaN/GaN double-channel HEMT (AlGaN-GDC-HEMT) and the AlN-GDC-HEMT. Two quantum wells are formed in both devices, leading to distinct double peak features in transconductance and cut-off frequency plots, highlighting efficient interchannel connection behavior. The study investigates the relative performance of AlN-GDC-HEMT and AlGaN-GDC-HEMT, exploring the influence of gate recess length (L _R ) and top barrier thickness. Additionally, the scaling behavior of the HEMTs is examined with varying gate lengths (L _G ). Furthermore, the impact of gate engineering and lateral scaling on both devices’ DC/RF behavior is explored. Extensive comparative analysis shows that the AlN-GDC-HEMT outperforms the conventional AlGaN-GDC-HEMT, mainly attributed to AlN’s higher polarization (spontaneous) density and its wider bandgap. The optimized AlN-GDC-HEMT with L _G = 40 nm, L _GS = 250 nm, and L _GD = 400nm exhibits superior performance resulting in transconductance (G _M ) values of 203.1 and 787.5 mS/mm at two peaks, an I _{DS_peak} of 1.97 A/mm, I _{DS_sat} of 3.18 A/mm, and the highest f _T derived from the left and right peaks was 285.1 and 416.8 GHz, respectively. The promising results from this first investigation indicate the potential and applicability of AlN-GDC-HEMTs in future RF power amplifiers.

Industries including energy production, automotive and aerospace has seen a tremendous increase in interest in high temperature electronics. There has been a lot of investigations done on wide bandgap materials because of the difficulties traditional electronics suffer at high temperatures, such as poor stability and increased leakage current. GaN-based power high electron mobility transistors (HEMTs) are a popular choice for a variety of power electronic applications due to their excellent efficiency and ability to deliver high power density. When it comes to power HEMTs, p-GaN gate technology is a reliable and affordable way to accomplish normally off (E-Mode) operation and guarantee fail-safe standards. This article critically reviews the advances and challenges in fabrication technologies, recent developments in materials, impact of gate first/gate last fabrication processes, gate contact effects, advances in etching techniques and annealing/plasma treatment effects in the development of p-GaN Gated E-Mode AlGaN/GaN RF Power HEMTs.

The relentless advancement of the semiconductor industry continues to be fueled by the pursuit of enhanced transistor performance. As CMOS technology undergoes aggressive scaling to enable higher integration densities in modern integrated circuits (ICs), there arises a pressing demand for novel device architectures that can minimize cell area without compromising functionality. The complementary-field-effect-transistor (CFET) is emerging as a leading contender to succeed gate-all-around (GAA) FETs beyond the 2-nm technology node, offering a compelling pathway to sustain Moores Law into the next era of scaling. Unlike forksheet FET (FSFET) architectures, where nFET and pFET devices are laterally separated, CFETs adopt a vertically stacked configuration. This vertical integration minimizes the required device footprint, constrained primarily by cell height rather than horizontal spacing. As a result, CFETs not only enhance the effective channel width and drive current but also offer the potential for up to a twofold increase in integration density compared to conventional CMOS technologies. This review explores recent advances in CFET architectures, fabrication progress, and associated challenges, exciting prospects in IC design enabled by CFET’s compact structure and vertical integration. Finally, the article highlights critical reliability concerns, emphasizing the need for continued innovation to ensure robust device performance. CFET stands at the forefront of next-generation transistor technologies.