Interleaving technique is used in some applications due to its advantages regarding filter reduction, dynamic response, and power management. In dual battery system vehicles, the bidirectional dc-dc converter takes advantage of this technique using three-to-five paralleled buck stages. In this paper, we propose the use of a much higher number of phases in parallel together with digital control. It will be shown that this approach opens new possibilities since changes in the technology are possible. Thus, two 1000-W prototypes have been designed using surface mount technology devices (SO-8 transistors). An additional important feature is that due to the accuracy of the digital device [field-programmable gate array (FPGA)], current loops have been eliminated, greatly simplifying the implementation of the control stage

Nowadays, most digital controls for power converters are based on DSPs. This paper presents a field programmable gate array (FPGA) based digital control for a power factor correction (PFC) flyback AC/DC converter. The main difference from DSP-based solutions is that FPGAs allow concurrent operation (simultaneous execution of all control procedures), enabling high performance and novel control methods. The control algorithm has been developed using a hardware description language (VHDL), which provides great flexibility and technology independence. The controller has been designed as simple as possible while maintaining good accuracy and dynamic response. Simulations and experimental results show the feasibility of the method, opening interesting possibilities in power converters control.

This paper proposes a new digital pulsewidth modulation (DPWM) architecture that takes advantage of the field-programmable gate array's (FPGA) advanced characteristics, especially the delay-locked loop (DLLs) present in almost every FPGA. The proposed DPWM combines a synchronous (counter-based) block with an asynchronous block for increased resolution without unnecessarily increasing the clock frequency. The experimental results show an implementation in a low-cost FPGA (Xilinx Spartan-3) that uses an external 32 MHz clock for a final time resolution under 2 ns.

Debugging digital controllers for power converters can be a problem because there are both digital and analog components. This paper focuses on debugging digital controllers to be implemented in Field Programmable Gate Arrays or Application Specific Integrated Circuits, which are designed in hardware description languages. Four methods are proposed and described. All of them allow simulation, and two methods also allow emulation-synthesizing the model of the converter to run the complete closed-loop system in actual hardware. The first method consists in using a mixed analog and digital simulator. This is the easiest alternative for the designer, but simulation time can be a problem, specially for long simulations like those necessary in power factor correction or when the controller is very complex, for example, with embedded processors. The alternative is to use pure digital models, generating a digital model of the power converter. Three methods are proposed: real type, float type and fixed point models (in the latter case including hand-coded and automatic-coded descriptions). Float and fixed point models are synthesizable, so emulation is possible, achieving speedups over 20 000. The results obtained with each method are presented, highlighting the advantages and disadvantages of each one. Apart from that, an analysis of the necessary resolution in the variables is presented, being the main conclusion that 32-bit floating point is not enough for medium and high switching frequencies.

A new digital control technique for power factor (PF) correction is presented. The main novelty of the method is that there is no current sensor. Instead, the input current is digitally rebuilt, using the estimated input current in the current loop. The circuit measures the input and output voltage by means of low cost ad hoc analog-to-digital converters (ADCs). Taking advantage of the slow dynamic behavior of these voltages, almost completely digital ADCs have been designed, leaving only a comparator and an RC filter in the analog part. Avoiding measuring current can provide a significant advantage compared to analog controllers and this also helps to reduce the total cost. The ultimate objective is to obtain a low-cost digital controller that can be easily integrated as an intellectual property (IP) block into a field-programmable gate array, or an application-specific integrated circuit. The experimental results show a reasonably high PF, despite not measuring the input current, and therefore the feasibility of the method.