Debugging digital controllers for power converters can be a problem because there are both digital and analog components. This paper focuses on debugging digital controllers to be implemented in Field Programmable Gate Arrays or Application Specific Integrated Circuits, which are designed in hardware description languages. Four methods are proposed and described. All of them allow simulation, and two methods also allow emulation-synthesizing the model of the converter to run the complete closed-loop system in actual hardware. The first method consists in using a mixed analog and digital simulator. This is the easiest alternative for the designer, but simulation time can be a problem, specially for long simulations like those necessary in power factor correction or when the controller is very complex, for example, with embedded processors. The alternative is to use pure digital models, generating a digital model of the power converter. Three methods are proposed: real type, float type and fixed point models (in the latter case including hand-coded and automatic-coded descriptions). Float and fixed point models are synthesizable, so emulation is possible, achieving speedups over 20 000. The results obtained with each method are presented, highlighting the advantages and disadvantages of each one. Apart from that, an analysis of the necessary resolution in the variables is presented, being the main conclusion that 32-bit floating point is not enough for medium and high switching frequencies.

This paper aims to compare different design alternatives of hardware-in-the-loop (HIL) for emulating power converters in Field Programmable Gate Arrays (FPGAs). It proposes various numerical formats (fixed and floating-point) and different approaches (pure VHSIC Hardware Description Language (VHDL), Intellectual Properties (IPs), automated MATLAB HDL code, and High-Level Synthesis (HLS)) to design power converters. Although the proposed models are simple power electronics HIL systems, the idea can be extended to any HIL system. This study compares the design effort of different coding methods and numerical formats considering possible synthesis tools (Precision and Vivado), and it comprises an analytical discussion in terms of area and speed. The different models are synthesized as ad-hoc modules in general-purpose FPGAs, but also using the NI myRIO device as an example of a commercial tool capable of implementing HIL models. The comparison confirms that the optimum design alternative must be chosen based on the application (complexity, frequency, etc.) and designers’ constraints, such as available area, coding expertise, and design effort.

This is the author’s version of a work that was accepted for publication in Measurement. Changes resulting from the publishing process, such as peer review, editing, corrections, structural formatting, and other quality control mechanisms may not be reflected in this document. Changes may have been made to this work since it was submitted for publication. A definitive version was subsequently published in Measurement, Vol. 45, Issue 3, (2012) DOI: http://dx.doi.org/10.1016/j.measurement.2011.12.002This work presents a low cost 3-D location system based on ultrasonics and implemented with low-cost FPGAs. The mobile nodes of the system use distance estimation to several anchor points in order to trilaterate their positions with an accuracy of few centimeters. The ultrasonic transducers are handled with an ad hoc conditioning circuit based on instrumental amplifiers which provides high amplification keeping low noise. The proposed system is autonomous so there is no need of an external PC or other devices. A prototype of the system has been attached to a mobile robot to check the viability of the location system in a real scenario.This work has been partially supported by the TEC2009-09871 project of the Ministerio de Ciencia e Innovacion, Spain

Traditional digital power factor correction (PFC) uses three sensors to measure the input and output voltages and the input current. Each sensor, especially the input current one, increases the cost of the system and generates power losses in case of resistive sensors. This paper presents a controller for boost PFC converters. It uses precalculated duty cycles generated offline, and applies them to the switch. In order to control the converter with nonnominal conditions, just one analog-to-digital converter (ADC) is used, which measures the output voltage. Measuring the average and the ripple of the output voltage with this ADC, the controller takes compensation action for changes in the input voltage but also in the load of the converter. The average value is used to control the input voltage changes, while the ripple value is used to control load changes. These two loops present low frequency bandwidth, so the ADC and the whole system can be low cost. Finally, a comparator is used to detect the zero-crossing of the input voltage, so the precalculated values are synchronized with the ac mains. In this way, the converter only uses one ADC and one comparator, both with low bandwidth. Results show that high power factor and normative compliance are reached, even under nonnominal conditions.

This work proposes two methods to determine the resolution of state variables in models of switching-mode power converters. The target models are intended for hardware-in-the-loop, i.e., closed-loop emulation using a model of the power converter implemented in digital hardware with the controller in its final implementation. The focus here is on the resolution of fixed-point models, although the results can also be applied to the significand resolution in floating-point representation. The first method is based on the simulation, provides the designer with the optimum resolution values, and guarantees that using the resolution, the converter will behave as it was specified. The second method is fast but conservative, intended for applications without hard constraints of area and speed. Despite the simplicity of the second method, its results, although slightly overestimated, have been demonstrated to be correct by the results of the first method. A boost converter for the power factor correction is used as an application example. As the converter model is intended for field-programmable gate array implementation, its area and maximum clock frequency are also analyzed. In this application example, the results show that the area grows linearly with the number of bits of each state variable, and the clock frequency is dominated by the width of one of the variables.