Renewable energy (RE) resources have reached the top-notch state in satisfying the energy demands of recent days. Solar photovoltaic (PV) is considered as a clean form of energy among the various RE resources. A novel single-phase grid-integrated solar PV system with Re-lift Luo converter with aid of a chicken swarm (CS) optimization algorithm is presented. The Re-lift Luo converter is implemented as it has maximum power density, extreme efficacy, high-voltage-gain ratio, and reduced switching losses. Since the PV output is intermittent, the output of the converter also gets varied, which will be maintained constant by implementing a proportional–integral (PI)-based closed loop control through the optimized CS algorithm. The normalized output is further applied to the grid via single-phase voltage source inverter. A battery is utilized to store the daytime’s solar energy and discharges to the grid during the night time. The monitoring of the battery’s state of charge (SoC) is performed by recurrent neural network (RNN). A PI controller achieves the real and reactive grid side power control. The novelty of the proposed work is the utilization of three control strategies such as PI, CS, and RNN in improving the overall performance of a grid connected system in improving the power quality. Proper control and analysis of the converters and battery through intelligent controllers are the major objectives of the paper. The outcome of the proposed concept reigns in the improvement of power quality and the proper estimation of SoC, which was supported by the detailed simulation and experimental studies. The proposed configuration is verified by simulation in MATLAB/Simulink and also tested in a real-time experimental setup, and the obtained results are as per the IEEE standards.

In this work, a high step-up sextuple voltage boosting 13 switches – 13 level inverter (SVB-13S -13LI) structure was proposed through a pulse width modulation technique with selective harmonic elimination. This topology can deliver six times of voltage boosting capability. A single voltage source, 13 switches, two diodes, and three capacitors are utilized to obtain the objective of this research. This work carried out various tests on the proposed topology to find efficiency, voltage stress, total standing voltage, and voltage gain. The detailed comparative study of existing inverter topologies is tabulated to prove the proposed topology has a better performance. The main feature of this topology is six times voltage boosting, a minimum number of switches, less voltage stress, and a self-balanced floating capacitor. Further to isolate or eliminate the undesired low order harmonics the particle swarm optimization-based SHPWM Technique is used. For proving the above-mentioned merits, the simulation was carried out using MATLAB SIMULINK and their corresponding THD results are compared with different Modulation indexes. Also, experimental results are validated by the FPGA SPARTAN 6E controller and their cost function [CF] for the unit price ($) are compared with the state-of-art literature 13-level inverters.

A multilevel inverter plays a predominant role in improving the performance as well as efficiency of the inverter. In this study, the proposed idea of the selective harmonic elimination (SHE) for Duple Voltage Boosting nine-level inverter topology with fewer switching components possesses two times better voltage boosting capability than the considered conventional models. The proposed inverter comprises 12 power semiconductor switches, two capacitors, and a single diode, which is connected to a single dc (direct current) source. The duple 9-level topology has been studied and evaluated under different multicarrier PWM (pulse width modulation) techniques in order to obtain lw THD (total harmonic distortion), and the results proves that the Level Control PWM Technique exhibits a better THD value of 9.35%. To improve the quality of the output waveform, the SHE has been designed to fix the predominant harmonics so that the lower order harmonics are minimized to generate a lower THD. A detailed discussion has been made with the results of the proposed inverter THD, which are then compared with other nine-level inverters MATLAB/SIMULINK that has been used to perform the simulation of the duple model, and the obtained simulation results have been validated for different modulation indices. The FPGA SPARTAN 6E controller tests the experimental prototype of the nine-level inverter, and their cost function is represented in dollars, which is compared with the other similar nine-level inverters.