This paper presents a hardware implementation of a digital predistorter (DPD) for linearizing RF power amplifiers (PAs) for wideband applications. The proposed predistortion linearizer is based on a nonlinear auto-regressive moving average (NARMA) structure, which can be derived from the NARMA PA behavioral model and then mapped into a set of scalable lookup tables (LUTs). The linearizer takes advantage of its recursive nature to relax the LUT count needed to compensate memory effects in PAs. Experimental support is provided by the implementation of the proposed NARMA DPD in a field-programmable gate-array device to linearize a 170-W peak power PA, validating the recursive DPD NARMA structure for W-CDMA signals and flexible transmission bandwidth scenarios. To the best of the authors' knowledge, it is the first time that a recursive structure is experimentally validated for DPD purposes. In addition to the results on PA efficiency and linearity, this paper addresses many practical implementation issues related to the use of FPGA in DPD applications, giving an original insight on actual prototyping scenarios. Finally, this study discusses the possibility of further enhancing the overall efficiency by degrading the PA operation mode, provided that DPD may be unavoidable due to the impact of memory effects.

This paper presents a comparative study on the suitability of using Hammerstein or Wiener models to identify the power amplifier (PA) nonlinear behavior considering memory effects. This comparative takes into account the operational complexity regarding the identification process as well as their accuracy to follow the PA behavior. Both identified PA models will be used to estimate a Hammerstein based predistorter in order to see which model combination provides better linearization results. In addition, two adaptive algorithms for predistorting both PA models are compared in terms of accuracy and converge speed.

This paper presents a new 3-D behavioral model to compensate for the nonlinear distortion arising in concurrent dual-band (DB) Envelope Tracking (ET) Power Amplifiers (PAs). The advantage of the proposed 3-D distributed memory polynomial (3D-DMP) behavioral model, in comparison to the already published behavioral models used for concurrent dual-band envelope tracking PA linearization, is that it requires a smaller number of coefficients to achieve the same linearity performance, which reduces the overall identification and adaptation computational complexity. The proposed 3D-DMP digital predistorter (DPD) is tested under different ET supply modulation techniques. Moreover, further model order reduction of the 3D-DMP DPD is achieved by applying the principal component analysis (PCA) technique. Experimental results are shown considering a concurrent DB transmission of a WCDMA signal at 1.75 GHz and a 10-MHz bandwidth LTE signal at 2.1 GHz. The performance of the proposed 3D-DMP DPD is evaluated in terms of linearity, drain power efficiency, and computational complexity.

This paper presents an estimation/adaptation method based on the adaptive principal component analysis (APCA) technique to guarantee the identification of the minimum necessary parameters of a digital predistorter. The proposed estimation/adaptation technique is suitable for online field-programmable gate array or system on chip implementation. By exploiting the orthogonality of the resulting transformed matrix obtained with the APCA technique, it is possible to reduce the number of coefficients to be estimated which, at the same time, has a beneficial regularization effect by preventing ill-conditioning or overfitting problems. Therefore, this identification/adaptation method enhances the robustness of the parameter estimation and simplifies the adaptation by reducing the number of estimated coefficients. Due to the orthogonality of the new basis, these parameters can be estimated independently, thus allowing for scalability. Experimental results will show that it is possible to determine the minimum number of parameters to be estimated in order to meet the targeted linearity levels while ensuring a robust well-conditioned identification. Moreover, the results will show how thanks to the orthogonality property of the new basis functions, the coefficients of the digital predistorter can be estimated independently. This allows to tradeoff the digital predistorter adaptation time versus performance and hardware complexity.

This paper presents the design of a nonlinear autoregressive moving average (NARMA) digital adaptive predistorter (DAPD) for power amplifier (PA) linearization consisting of a low-complex closed-loop architecture. Both the predistortion function and the adaptation algorithm are fully implemented in a field-programmable gate array (FPGA) device, without the need for using any additional coprocessor. The proposed predistortion architecture is capable to compensate for both the PA nonlinear distortion and memory effects. Moreover, this DAPD allows almost real-time adaptation without interrupting the normal transmission. The computational complexity introduced by this DAPD is studied in this paper. The proposed theoretical design is implemented in an FPGA, whereas the linearization performance of the DAPD is validated through simulated and experimental results.

Over at least the last two decades, digital predistortion (DPD) has become the most common and widespread solution to cope with the power amplifier's (PA's) inherent linearity-versus-efficiency tradeoff. When compared with other linearization techniques, such as Cartesian feedback or feedforward, DPD has proven able to adapt to the always-growing demands of technology: wider bandwidths, stringent spectrum masks, and reconfigurability. The principles of predistortion linearization (in its analog or digital forms) are straightforward, and the linearization subsystem precedes the PA (a nonlinear function in a digital signal processor in the case of DPD or nonlinear device in the case of analog predistortion and counteracts the nonlinear characteristic of the PA. Some excellent overviews on DPD can be found in [1]-[4]. Let us now look at the challenges that DPD linearization has faced and will continue to face in the near future with 5G new radio (5G-NR).