CHANDRASEKAR ANURADHA

Mrs. CHANDRASEKAR ANURADHA

orcid

Research Focus & Metrics

Academic Career Length

8Years (2019-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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1 October 2024 in Indonesian Journal of Electrical Engineering and Computer Science
Verified
Journal Article
Open access
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CACHANDRASEKAR ANURADHA
CHANDRASEKAR ANURADHA
RRRathinam Anantha Raman
Rathinam Anantha Raman
GAGanesan Arunsankar
Ganesan Arunsankar
MJMaharajan Robinson Joel
Maharajan Robinson Joel
PSPitchamuthu Sathyanathan
Pitchamuthu Sathyanathan
SMSubbiah Murugan
Subbiah Murugan
Electronic devices and loads are very sensitive to the voltage disturbances like voltage sag and voltage swell. Significant financial losses and safety issues may emerge from voltage sags and interruptions, which can be caused by variables such as system breakdowns and load changes. In order to protect against voltage fluctuations and keep vital loads running, dynamic voltage restorers (DVRs) have become more popular. To mitigate the voltage disturbances, an interlined DVR (IDVR) using a Z-source inverter (ZSI) is developed to protect the sensitive devices and loads. Back-to-back DVR connects the distributed feeders with a common direct current (DC) link. The IDVR compensates for the sag voltage and supplies the energy to control the power flow. In addition, proposed a modified synchronous reference frame (MSRF)/direct quadrature theory, hysteresis controller, and proportional integral (PI) controller, which provides the required amount of control signals for a ZSI and voltage source inverter (VSI). MATLAB/Simulink validated the simulation results. The experimental findings show that the suggested system can be implemented successfully and is effective at reducing voltage dips and interruptions, allowing crucial loads to keep operating consistently and without interruption in residential as well as commercial environments.

11 January 2019 in Energies
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Journal Article
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CACHANDRASEKAR ANURADHA
CHANDRASEKAR ANURADHA
CNChellammal Nallaperumal
Chellammal Nallaperumal
MMMd Saquib Maqsood
Md Saquib Maqsood
SVS. Vijayalakshmi
S. Vijayalakshmi
An efficient way of synthesizing a three port non-isolated converter from a single-ended primary inductor converter (SEPIC) is proposed in this paper. The primary SEPIC converter is split into a source cell and a load cell. Two such source cells are integrated through direct current (DC) link capacitors with a common load cell to generate a three-port SEPIC converter. The derived converter features single-stage power conversion with reduced structural complexity and bidirectional power flow capability. For bidirectional power flow, it incorporates a battery along with an auxiliary photovoltaic source. Mathematical analyses were carried out to describe the operating principles and design considerations. Experiments were performed on an in-house-built prototype three-port unidirectional converter, and the results are presented to validate the feasibility of the designed converter.

27 September 2024 in Sustainability
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Journal Article
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CACHANDRASEKAR ANURADHA
CHANDRASEKAR ANURADHA
VSVijayalakshmi S
Vijayalakshmi S
NRNarayanamoorthi Rajamanickam
Narayanamoorthi Rajamanickam
MSMohammad Shorfuzzaman
Mohammad Shorfuzzaman
AEAhmed Mohamed Emara
Ahmed Mohamed Emara
A new four-port non-isolated SEPIC converter intended for hybrid renewable energy systems is presented in this study. The suggested converter minimizes space and expense by integrating two inputs and two outputs in a single-stage structure with fewer components. The converter retains important characteristics including continuous input current, buck/boost capability, non-inverting output, and enhanced power factor because it is based on the fundamental SEPIC topology. It effectively combines an energy storage system (ESS) with a variety of energy sources that have different voltage and current characteristics. The converter can be configured to operate in unidirectional or bidirectional topologies depending on whether storage elements are included. Performance is examined in two operating modes, with an emphasis on the ESS’s charging and discharging processes. System equations are produced by steady-state analysis, and the design of a closed-loop controller for accurate input power and output voltage regulation is informed by dynamic analysis performed with the state-space approach. Through real-time hardware implementation and MATLAB/Simulink simulations, the efficacy of the suggested design is verified, demonstrating the open-loop unidirectional topology’s theoretical and practical validity.

1 September 2022 in International Journal of Power Electronics and Drive Systems (IJPEDS)
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Journal Article
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SVSubramanian Vijayalakshmi
Subramanian Vijayalakshmi
VGVelappa Ganapathy
Velappa Ganapathy
CACHANDRASEKAR ANURADHA
CHANDRASEKAR ANURADHA
RIRaghavan Chandran Ilambirai
Raghavan Chandran Ilambirai
VGViswanathan Ganesh
Viswanathan Ganesh
In this paper, a standalone permanent magnet synchronous generator (PMSG) system is designed to generate power at maximum power point (MPP). The variable speed operation of wind energy conversion system consists of PMSG, controlled rectifier and voltage source inverter co to the load. Proportional integral (PI), sliding mode (SM), and feed forward neural network (FFNN) control strategies are applied in field oriented control (FOC) at generator side converter. A comparative study on power generated at maximum power point (MPP) is done with these controllers using simulation. Hill climb search (HCS) method is applied to attain MPP. Load side inverter control strategy involves the PI and SM controllers in order to maintain the unity power factor and to control the active and reactive power for nonlinear load. The control strategies are modelled and simulated with MATLAB/Simulink. The effectiveness of proposed control method is demonstrated using simulation results.

8 December 2025 in Engineering, Technology & Applied Science Research
Verified
Journal Article
Open access
CACHANDRASEKAR ANURADHA
CHANDRASEKAR ANURADHA
AMA. V. Mayakkannan
A. V. Mayakkannan
RVR. Vinodha
R. Vinodha
KRK. Narsimha Reddy
K. Narsimha Reddy
BAB. Annapurna
B. Annapurna
CSC. Srinivasan
C. Srinivasan
Routing in Wireless Sensor Networks (WSNs) is highly vulnerable due to the unreliable wireless medium and limited node resources. Routing attacks can severely degrade network performance. This paper proposes a Robust Security system using Reinforcement Learning (RSRL) and the Secure Hash Algorithm 512 (SHA-512) for secure and efficient routing in WSNs. The primary objective of the RSRL mechanism is to detect malicious nodes and enhance system security. In the RSRL mechanism, the Base Station (BS) performs aggregator verification using SHA-512 to ensure data integrity without burdening low-power sensor nodes. A Reinforcement Learning (RL) agent, executed at the BS, dynamically learns optimal policies to detect malicious sensor nodes based on node Response Time ( ), Consumed Energy ( ), and Loss Ratio ( ). The RSRL system selects reliable nodes for route selection to improve routing efficiency. The proposed RSRL model is implemented in Network Simulator 2.35. Simulation results demonstrate a 26.44% improvement in Packet Forwarding Ratio ( ) and 95% detection accuracy compared to a conventional secure routing mechanism. The results confirm that RSRL effectively mitigates routing attacks while maintaining high network performance.

5 August 2023
Verified
Book Chapter
Closed access
PDF file
CACHANDRASEKAR ANURADHA
CHANDRASEKAR ANURADHA
VSVijayalakshmi S
Vijayalakshmi S
VGViswanathan Ganesh
Viswanathan Ganesh
PRP. S. Ramapraba
P. S. Ramapraba