This paper presents a sub-μW ac-coupled reconfigurable front-end for invasive wideband neural signal recording. The proposed topology embeds filtering capabilities enabling the selection of different frequency bands inside the neural signal spectrum. Power consumption is optimized by defining specific noise targets for each sub-band. These targets take into account the spectral characteristics of wideband neural signals: local field potentials (LFP) exhibit 1/fx magnitude scaling while action potentials (AP) show uniform magnitude across frequency. Additionally, noise targets also consider electrode noise and the spectral distribution of noise sources in the circuit. An experimentally verified prototype designed in a standard 180 nm CMOS process draws 815 nW from a 1 V supply. The front-end is able to select among four different frequency bands (modes) up to 5 kHz. The measured input-referred spot-noise at 500 Hz in the LFP mode (1 Hz - 700 Hz) is 55 nV/√Hz while the integrated noise in the AP mode (200 Hz - 5 kHz) is 4.1 μ Vrms. The proposed front-end achieves sub-μW operation without penalizing other specifications such as input swing, common-mode or power-supply rejection ratios. It reduces the power consumption of neural front-ends with spectral selectivity by 6.1x and, compared with conventional wideband front-ends, it obtains a reduction of 2.5x.

This work introduces a tunable technique to push the low-frequency corner ($f_L$) of capacitively coupled instrumentation amplifiers (CCIAs) to the sub-mHz range for emerging biosensing applications. The proposed approach combines Complementary Transimpedance Boosting (CTB) to limit the DC feedback current and segmented duty-cycled resistors (SDR) for tunable resistance. The CTB-SDR technique achieves a stable effective post-layout pseudo-resistance of $535.8 \mathrm{T}\Omega$, equivalent to $f_L=660 \mu \mathrm{Hz}$ while occupying $0.062 {\mathrm{mm}}^2$ in a 180 nm process. According to JESD91 standards, it shows a standard deviation of $0.19 \mathrm{mHz}$ under post-layout Monte Carlo + process analysis, $1.1\%$ spread under voltage variations $(\pm 5.56\% V_{DD})$ and $6.2\%$ under temperature variations $(-20 °\mathrm{C}, 27 °\mathrm{C},$ and $60 °\mathrm{C})$. In addition, duty-cycling calibration can compensate for worst-case process corner variations and mismatch-induced feedback instability.