To clarify the current research situation and offer a better understanding of the reliability for silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors ( mosfet s), a comparison among the reliability mechanisms between planar-gate (PG) and trench-gate (TG) SiC power mosfet s, which have not been comprehensively summarized, is made in this article. The latest studies focusing on the reliability issues of commercial SiC mosfet products, including the PG device, the double-trench device and the asymmetric TG device, are reviewed. For the existing of the gate trenches and the unique structures protecting them, SiC TG mosfet s express quite different instability phenomena from the PG ones under various ultimate and long-term electro-thermal stresses. The influences of these stresses closely related to the practical operation conditions on SiC power mosfet s, including the avalanche stress, the short-circuitstress, the surge current stress of the body diode, and the switching stress, are discussed and reviewed in details.

Degradations of dynamic characteristics for SiC power MOSFETs under repetitive avalanche shocks are investigated in details. With the help of Silvaco TCAD simulations, Cg-Vg measurement and three-terminal CP test, the main damaged position is demonstrated to be the SiC/SiO2 interface along JFET region instead of the body diode where most avalanche current paths through. Dominant avalanche degradation mechanism is then confirmed to be the injection of holes into the gate oxide above JFET region. Since the channel region and the main junction of body diode are not seriously damaged by avalanche stress, static parameters all remain stable. Meanwhile, due to the injection of holes, the depletion layer beneath JFET region gets thinner, resulting in the increase of Cgd under low Vds bias condition. It further takes responsibilities for the increments in Ciss, Coss and Crss. Moreover, it results in the extension of Miller plateau. Therefore, increase of gate charge and delay of turn-off time after being stressed by repetitive avalanche shocks are monitored. Moreover, turn-on and turn-off dissipated energies after different UIS stress cycles are extracted. They are rarely influenced by the stress for the overlapping areas of voltage and current during switching procedures are relatively stable.

This letter firstly reveals the single pulse unclamped-inductive-switching (UIS) withstanding physics and failure mechanism for p-GaN high electron mobility transistor (HEMT) with Schottky type gate contact. Unlike Si/SiC-based devices, the p-GaN HEMT withstands the surge current from load inductor by storing the energy into the output capacitance of the device, rather than dissipating the energy by avalanche process. To describe the UIS process, physics-based models are proposed. Also, by the simulations and de-cap/de-layer experiments, the failure mechanism is presented as a different manner compared with Si/SiC-based devices. The high voltage during the UIS process introduces high electric field near the drain contact, which leads to the inverse-piezoelectric effect, then bringing the rise-up of the leakage current and high power dissipation. As a result, the region near drain contact is burned by thermal runaway. Moreover, it is demonstrated that higher bus voltage and larger load inductance will increase the UIS-induced failure risk, while the gate resistance, turn-off gate voltage and ambient temperature exhibit little influences upon the UIS withstanding capability of the device.

This article makes the comparisons on the behaviors of three types of commercial GaN power switching devices, including Schottky gate p-GaN high electron mobility transistor (HEMT), ohmic gate p-GaN HEMT with hybrid drain, and Cascode GaN device, under single-pulse and repetitive unclamp-inductive-switching (UIS) conditions by experiments and simulations. It shows that all the three types of GaN devices withstand the UIS stress by storing energy in parasitic capacitances rather than by avalanche process, which is a different phenomenon compared with traditional Si/SiC devices. However, the failure phenomena under single-pulse UIS condition are different. For the two types of p-GaN gate devices, the inverse-piezoelectric induced punch-through makes the burnout under drain contact region. For the Cascode device, the breakdown of the inner Si device dominates the failure. As for the behaviors under repetitive UIS stresses, p-GaN gate device with hybrid drain performs the best, Schottky gate p-GaN HEMT shows the most serious electrical performance degradations due to the trapping effects and carrier storage phenomena, Cascode GaN device exhibits stable threshold voltage and acceptable degradations of on -state resistance due to the existence of inner Si device.

In this work, a high-voltage amorphous In-Ga-Zn-O (a-IGZO) thin-film-transistors (TFTs) with the stair gate-dielectric at the drain side were demonstrated. The electrical properties of the proposed TFTs were comprehensively investigated. The breakdown voltage ( V _BD ) was significantly enhanced, and the V _BD of over 60 V is achieved in the TFT with the stair length ( L _stair ) of 3 μm. The TCAD simulation and emission microscope (EMMI) measurements are performed to reveal the working and breakdown mechanisms of the proposed stair gate-dielectric TFTs. The descending electron current density in the channel lowers the stair-gate TFTs' ON-current. Meanwhile, the stair-gate-dielectric region endures a strong electric field and improves the V _BD of the device. Finally, the exponential trade-off relationship between the V _BD and the ON-state resistance ( R _ON ) was established.

In this letter, comprehensive static and dynamic electrical parameter degradations of p-GaN gate high electron mobility transistor (HEMT) under repetitive short-circuit (SC) stresses are presented. Meanwhile, the mechanisms behind those degradations are first distinguished. The results indicate that both the gate region and the access region are damaged by the SC stresses, dominating the shifts of electrical parameters. Moreover, a method by modeling the output capacitance is proposed to characterize damages in access region. Finally, the switching characteristics after the stresses are investigated, it is found that the switching speed benefits from the increase in the gate leakage current. Considering the aging of p-GaN HEMT under long-term operation conditions, all the damages brought by repetitive SC stresses should be eliminated to prevent the failure of p-GaN gate and the increase in conduction loss.