To clarify the current research situation and offer a better understanding of the reliability for silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors ( mosfet s), a comparison among the reliability mechanisms between planar-gate (PG) and trench-gate (TG) SiC power mosfet s, which have not been comprehensively summarized, is made in this article. The latest studies focusing on the reliability issues of commercial SiC mosfet products, including the PG device, the double-trench device and the asymmetric TG device, are reviewed. For the existing of the gate trenches and the unique structures protecting them, SiC TG mosfet s express quite different instability phenomena from the PG ones under various ultimate and long-term electro-thermal stresses. The influences of these stresses closely related to the practical operation conditions on SiC power mosfet s, including the avalanche stress, the short-circuitstress, the surge current stress of the body diode, and the switching stress, are discussed and reviewed in details.

Degradations of dynamic characteristics for SiC power MOSFETs under repetitive avalanche shocks are investigated in details. With the help of Silvaco TCAD simulations, Cg-Vg measurement and three-terminal CP test, the main damaged position is demonstrated to be the SiC/SiO2 interface along JFET region instead of the body diode where most avalanche current paths through. Dominant avalanche degradation mechanism is then confirmed to be the injection of holes into the gate oxide above JFET region. Since the channel region and the main junction of body diode are not seriously damaged by avalanche stress, static parameters all remain stable. Meanwhile, due to the injection of holes, the depletion layer beneath JFET region gets thinner, resulting in the increase of Cgd under low Vds bias condition. It further takes responsibilities for the increments in Ciss, Coss and Crss. Moreover, it results in the extension of Miller plateau. Therefore, increase of gate charge and delay of turn-off time after being stressed by repetitive avalanche shocks are monitored. Moreover, turn-on and turn-off dissipated energies after different UIS stress cycles are extracted. They are rarely influenced by the stress for the overlapping areas of voltage and current during switching procedures are relatively stable.

This letter introduces a new physics-based SPICE modeling method for the dynamic on -state resistance ( R _on,dy ) of gallium nitride based p-type gate power high electron mobility transistors (p-GaN HEMTs). To describe the continuous variations of R _on,dy , a time-resolved electron mobility variation (Δ μ _eff ) model is proposed. Physical parameters including activation energy and voltage acceleration factor of traps in p-GaN HEMTs are extracted as the model parameters. Then, to achieve the goal of simulating R _on,dy , the proposed Δ μ _eff model is incorporated into the surface potential based advanced SPICE model for GaN HEMT. Simulative results prove the proposed models can predict the R _on,dy induced power loss.

This letter proposes a monolithically integrated bidirectional gate electrostatic discharge protection scheme for p-GaN power high-electron-mobility transistors (HEMTs), in which a dual-gate HEMT is designed as the discharging transistor. With this protection scheme, the forward/reverse transmission line pulsing failure current is enhanced from 0.156 A/0.08 A to 1.36 A/5.26 A, almost without sacrificing performances of the p-GaN power HEMT. Thanks to the bidirectional switching characteristics of the dual-gate device by sharing the drift region, only one discharging transistor is required in the scheme; as a result, the area of this protection scheme can be effectively saved by 40.8% compared to state-of-the-art scheme with the same protection capability.

In this paper, we compare a new 1.2 kV rated 4H-SiC split-gate (SG) MOSFET with the conventional planar-gate (PG) MOSFETs. Both structures were fabricated with the same design rules and process platform. Therefore, the structures have similar electrical parameters, such as ON-state drain-source resistance (R_ON), breakdown voltage (BV), threshold voltage (V_th), and body diode forward voltage (V_SD). It is shown that the C_iss/C_oss/C_rss capacitances of the SG-MOSFET can be reduced by 7%/8%/17%, respectively, compared with PG-MOSFET. It is also shown that the SG-MOSFET has the potential to reduce switching losses without compromising the static performance. Moreover, it maintains the robustness of the device, and an optimized layout design with spaced holes in the gate poly is adopted. Therefore, there is no obvious degradation between the SG-MOSFET and the PG-MOSFET in terms of avalanche and short-circuit endurance capabilities.

The variations in the degradation of electrical characteristics resulting from different device structures for trench-gate SiC metal-oxide-semiconductor field effect transistors (MOSFETs) are investigated in this work. Two types of the most advanced commercial trench products, which are the asymmetric trench SiC MOSFET and the double-trench SiC MOSFET, are chosen as the targeted devices. The discrepant degradation trends caused by the repetitive avalanche stress are monitored. For the double-trench device, the conduction characteristic improves while the gate-drain capacitance (C_gd) increases seriously. It is because positive charges are injected into the bottom gate oxide during the avalanche process, which are driven by the high oxide electronic field (E_ox) and the high impact ionization rate (I.I.) there. Meanwhile, for the asymmetric trench SiC MOSFET, the I–V curve under the high gate bias condition and the C_gd remain relatively stable, while the trench bottom is well protected by the deep P+ well. However, it’s threshold voltage (V_th) decreases more obviously when compared with that of the double-trench device and the inclined channel suffers from more serious stress than the vertical channel. Positive charges are more easily injected into the inclined channel. The phenomena and the corresponding mechanisms are analyzed and proved by experiments and technology computer-aided design (TCAD) simulations.