To clarify the current research situation and offer a better understanding of the reliability for silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors ( mosfet s), a comparison among the reliability mechanisms between planar-gate (PG) and trench-gate (TG) SiC power mosfet s, which have not been comprehensively summarized, is made in this article. The latest studies focusing on the reliability issues of commercial SiC mosfet products, including the PG device, the double-trench device and the asymmetric TG device, are reviewed. For the existing of the gate trenches and the unique structures protecting them, SiC TG mosfet s express quite different instability phenomena from the PG ones under various ultimate and long-term electro-thermal stresses. The influences of these stresses closely related to the practical operation conditions on SiC power mosfet s, including the avalanche stress, the short-circuitstress, the surge current stress of the body diode, and the switching stress, are discussed and reviewed in details.

Four-switch buck-boost (FSBB) converter is widely used in battery applications due to the simple structure and the excellent performance of both voltage step-up and step-down. With the quadrangle control method, FSBB converter can realize zero voltage switching (ZVS) of all power switches, and thus can adapt to the high-frequency trends. However, the conventional quadrangle control method has two problems: 1) the efficiency degradation caused by the large root mean square (RMS) current of the inductor, and 2) the instability caused by the coupling relationship between multiple control variables. In this article, an improved quadrangle control method is proposed to solve the two problems, making FSBB converter a good candidate for high-frequency battery applications. First, the loss analysis is built to determine the relationship between loss and the control variables. Then, the conditions to achieve the minimum loss are obtained. Second, the decoupling compensation strategy is applied to free the coupling relationship to improve the stability. The proposed strategy can achieve three control goals: 1) ZVS of all power switches; 2) minimize the total loss; and 3) stable closed-loop system. Finally, a 1MHz 280W FSBB prototype is built to verify the proposed control method. The prototype achieves all control goals and 98.1% peak efficiency.

The degradations of electrical parameters for silicon carbide power MOSFETs under repetitive short-circuit (SC) stress are investigated in detail in this paper. It demonstrates that the generation of negative charges along the gate-oxide interface of the channel region is the dominant degradation mechanism, which results in the increase in the threshold voltage (Vth) and the rise of on-state resistance (Rdson) under low gate voltage bias condition. Furthermore, degradations of dynamic characteristics including gate charge (Qg) and switching behaviors of the device after the repetitive SC stress are extracted and analyzed for the first time. It illustrates that the increased Vth contributes to the rise of the Miller plateau voltage (Vgp), which further leads to the increase in gate-source charge (Qgs). Meanwhile, the increase in the turn-on time and the reduction of turn-off time are observed, which are also resulted from the positive shifts of Vth and Vgp, leading to the rise of turn-on switching energy (Eon) and the decline of turn-off switching energy (Eoff), respectively.

In this paper, the electrical parameter degradations of high-voltage 4H-SiC MOSFETs under repetitive unclamped-inductive-switching (UIS) stresses were investigated experimentally. The holes injection and trapping into the gate oxide above the JFET region is identified to be the main degradation mechanism, resulting in the increase of OFF-state drain-source leakage current (I _DSS ) and the decrease of ON-state resistance (R _dson ). However, during the repetitive UIS stresses, there is not obvious degradation observed for the threshold voltage (V _th ) of the device. Moreover, three improved SiC MOSFETs structures, one with step gate oxide above the JFET region, one with step p-body region, and another one with floated shallow p-well in the middle of JFET region, were proposed to reduce the degradations under the repetitive UIS stresses.

Two-stage cascade architecture is widely used in the modular power supply applications. In order to reduce the additional component number caused by the cascading structure, power switch integration technique is proposed in numerous literature. However, the power switch integration leads to both the efficiency degradation and the abnormal gain of the stage employed. In this paper, the four-switch noninverting buck-boost converter is merged with the LLC resonant converter. The proposed integration method has no awful influence on the efficiency and the gain of the LLC stage. Meanwhile, the soft switch capability of the integrated bridge can be enhanced due to the accumulation of the two current of the buck-boost stage and the LLC stage during dead-time. Moreover, the current of the two-stage will commutate to cancel out with each other during the conduction period, reducing the conduction loss and improving the overall efficiency. The benefits of the integrated bridge make the proposed converter appropriate for the high-frequency and highefficiency application. Finally, a 720W 1MHz prototype is built to prove the performance of the proposed converter. The prototype achieves a peak efficiency of 96.4% and the input voltage range of 250-420V.

Degradations of dynamic characteristics for SiC power MOSFETs under repetitive avalanche shocks are investigated in details. With the help of Silvaco TCAD simulations, Cg-Vg measurement and three-terminal CP test, the main damaged position is demonstrated to be the SiC/SiO2 interface along JFET region instead of the body diode where most avalanche current paths through. Dominant avalanche degradation mechanism is then confirmed to be the injection of holes into the gate oxide above JFET region. Since the channel region and the main junction of body diode are not seriously damaged by avalanche stress, static parameters all remain stable. Meanwhile, due to the injection of holes, the depletion layer beneath JFET region gets thinner, resulting in the increase of Cgd under low Vds bias condition. It further takes responsibilities for the increments in Ciss, Coss and Crss. Moreover, it results in the extension of Miller plateau. Therefore, increase of gate charge and delay of turn-off time after being stressed by repetitive avalanche shocks are monitored. Moreover, turn-on and turn-off dissipated energies after different UIS stress cycles are extracted. They are rarely influenced by the stress for the overlapping areas of voltage and current during switching procedures are relatively stable.