This work investigates bias-temperature instability (BTI) in 1700 V 4H-SiC MOSFETs under realistic 1 MHz switching conditions with simultaneous gate and drain stress. Threshold-voltage measurements reveal that the degradation does not follow the classical Reaction–Diffusion behavior typically assumed for silicon devices. Instead, the power-law exponent n shows a clear increase at the largest negative gate bias (−10 V), indicating a field-driven trap-generation mechanism. Temperature-dependent stress tests further show a negative activation energy (−0.466 eV), consistent with degradation accelerating at lower temperatures due to suppressed detrapping. The results demonstrate that conventional silicon BTI models cannot be directly applied to SiC technologies and that fixed-n lifetime extrapolation leads to significant errors. A bias-dependent, field-driven framework for estimating time-to-failure is proposed, offering more accurate and practical reliability prediction for high-power SiC converter applications.
1 October 2024 in IEEE Transactions on Electron Devices
In this article, an artificial neural network (ANN) augmented compact model is developed for the fast uncertainty quantification (UQ) of GaN high electron mobility transistors (HEMTs). The proposed model consists of a space mapping neural network (SMNN) that maps the uncertain geometrical, physical, material, bias, and trap-related parameters to the input features of a conventional GaN HEMT compact model. Traditionally, compact models demand repetitive feature retuning for any change in the trap energy levels and/or trap densities leading to a high computational time cost. The proposed augmentation maps the one-time calibrated compact model output to the true device responses for any variability in the trap energy levels and/or trap densities. Therefore, the proposed model can capture the impact of a wide distribution of trap-related parameters on GaN HEMT responses more efficiently than the conventional compact models. Numerical examples are provided to perform device- and circuit-level UQ using the proposed framework.